STWBC2-HP datasheet(59/96 Pages) STMICROELECTRONICS

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Figure 58. NVM block diagram overview

Note:

For readability reasons, the block diagram shows only the most relevant signals.

2.2.11.3.1

NVM details operation

The memory command requests are set through the SPI register signals NVM_HW_REQ and NVM_PC_REQ

belonging to register NVM_CTRL_0, then the controller sets the NVM_BUSY bit notifying an access in progress

or the NVM_ABRT bit in case of an ongoing transaction triggering the FSM flow execution. As soon as the NVM

operation is completed the NVM_EOC status bit is set and the NVM_BUSY flag is reset. All status bits are reset

by the NVM_STS_CLR command bit.

The memory command operations are controlled by an internal FSM logic which generates the STANDBY

command at the beginning and at the end of any user command sequences to meet the NVM memory access

requirements.

The FSM works according to an embedded counter timer count value (the timer is enabled/disabled directly

from the FSM logic) an additional long timer counter is used to control the modify timing access used during

SOFT-ERASE, ERASE and WORD-PROGAM commands.

2.2.11.3.2

NVM clock operation

The NVM clock frequency is configured through the NVM_CLK_DIV[1:0] bit fields of register NVM_CTRL_2. In

order to minimize the dynamic power consumption, the CLK_NVM is enabled only during the memory command

execution. The CLK_NVM operating frequency should be configured in a range between 4 MHz to 5 MHz; the

clock line is generated by a programmable clock divider logic interconnected to the NVM controller “afe_clk” clock

signal.

Table 43 summarizes the NVM legal clock frequency configurations.

Table 43. NVM clock frequency configuration overview

AFE_CLK

NVM_CLK_DIV[1:0]

CLK_NVM

Comment

20 MHz

5 MHz

ATE_CLK

16 MHz

4 MHz

AFE_CLK

10 MHz

5 MHz

ATE_CLK

8 MHz

4 MHz

AFE_CLK

STWBC2-HP

Digital AFE functions

DS13825 - Rev 1.0

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