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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STWBC2-HP датащи(PDF) 62 Page - STMicroelectronics |
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STWBC2-HP датащи(HTML) 62 Page - STMicroelectronics |
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62 / 96 page  2.2.12.3 Functional description Figure 59 shows the RCC block diagram. Figure 59. RCC block diagram 2.2.12.4 Reset functionality The block uses the ASYNC_NRST_0 signal coming from the pad and the ASYNC_NRST_1 provided by a GPIO driven from the FW application. These signals concur to generate the internal main reset signal in the two clock domains. A selective reset may be generated by SW in order to reset a specific IP without impacting the functionalities of other circuits. Figure 60 shows an outline view of the AFE reset circuit. Figure 60. Reset circuit overview Note: 1. SYNC_NRST_PLL_0 used for DOMAIN_NRST_OUT[13-15 2. PLL_CLK_GATED[0] used for DOMAIN_NRST_OUT[13-15] Note that the reset scheme is intended to show the circuit functionality and may be not aligned with the RTL implementation. STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 62/96 |
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