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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STWBC2-HP датащи(PDF) 72 Page - STMicroelectronics |
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STWBC2-HP датащи(HTML) 72 Page - STMicroelectronics |
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72 / 96 page  Figure 76. Page Register sub-block diagram overview The register sub-system is arranged around a page select cell and a single register located at address 0. The address 0 register is always accessed since the PB bus address is 0. This register has the following layout: Offset: 0x00 Default Value: 0x00 PAGE_REGISTER Control Interface 7 6 5 4 3 2 1 0 auto_inc RFU page_sel R/W R R/W R/W R R/W • auto_inc bit: this bit is provided to the SPI slave interface to control the auto increment of access address. • page_sel[2:0]: this vector is provided to the page select cell in order to select a page of registers. 2.2.14.4 Operating parameters Table 51 summarizes the IP functional operating parameters: Table 51. Register subsystem operating parameters Parameter Value Bus data width 8 bits Bus address width 7 bits 2.2.14.5 Configuration register overview Table 52 shows the list of Register subsystem configuration registers overview: STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 72/96 |
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