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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STWBC2-HP датащи(PDF) 63 Page - STMicroelectronics |
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STWBC2-HP датащи(HTML) 63 Page - STMicroelectronics |
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63 / 96 page  2.2.12.5 Clock functionality The AFE companion DIE has two asynchronous clock lines. • The main clock is originated by the MCU companion device after the initialization. The clock is interconnected to a programmable divisor logic to select the AFE target operating frequency in a range of 8 – 16 MHz. The main clock is supplied to the PLL reference clock line in a range of 8 – 18 MHz. • The high-speed clock is provided by a PLL phase locked circuit interconnected to a 17 phase DLL which provides 17 clocks up to 40 MHz Note: After reset the CLK_OUT is equal to the CLK_IN. Figure 61 shows the clock divisor circuit overview. Figure 61. Clock divisor circuit overview Figure 62 shows the clock enable circuit overview. Figure 62. Clock enable circuit overview Note: 1. SYNC_NRST_PLL_0 used for DOMAIN_CLK_OUT[13-15] 2. PLL_CLK_GATED[0] used for DOMAIN_CLK_OUT[13-15] 3. The clock enable controllability of PLL_CLK_GATED[15] is reserved 4. PLL_CLK_GATE[16:0] clock lines are directly interconnected to the HR-PWM IP 2.2.12.5.1 DMD clock Figure 63 shows the clock circuit used to generate the demodulation comparator auto-zero offset functionality. STWBC2-HP Digital AFE functions DS13825 - Rev 1.0 page 63/96 |
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