8.2.2 Design Requirements

This design uses the parameters listed in Design Requirements.

Table 8-1. Design Parameters

PARAMETER

VALUE

Input voltage

10.8 V – 13.2 V

Output Voltage

3.3 V

Output current

35 A

Switching frequency

800 kHz

8.2.3 Detailed Design Procedure

This design example leverages the requirements for the TPS548C26EVM. The default settings for this device

are optimal for this application. The following steps illustrate how to select key components.

8.2.3.1 Inductor Selection

In general, a smaller inductance increases loop bandwidth leading to better transient response at the expense of

higher current and voltage ripple. The inductor must be selected such that the transient performance and ripple

requirements are balanced for a particular design. The recommendation is that the inductor ripple current is kept

within the range of 20% to 40% of the desired output current. In this example, a 400-nH, 0.8-mΩ inductor is

used.

8.2.3.2 Input Capacitor Selection

Input capacitors must be selected to provide reduction in input voltage ripple and high-frequency bypassing,

which in return reduces switching stress on the power stage MOSFETs internal to the device. In this example, a

0.1-µF, 25-V, 0402 ceramic capacitor must be placed as close as possible to pin 20 of the device on the same

layer as the IC on the PCB. In addition, 6pcs 10-µF ceramic capacitors are used and an optional 270-µF bulk

capacitor is used on the input.

8.2.3.3 Output Capacitor Selection

To meet the output voltage ripple and load transient requirements, use a 1-µF and 2pcs 22-µF ceramic

capacitors local to the output of the inductor. Additionally, use 2pcs 220-µF bulk capacitors on the top-side

of the PCB combined with 4pcs 22-µF ceramic capacitors on the bottom-side of the PCB.

8.2.3.4 VCC and VRDV Bypass Capacitor

Connect a 2.2-µF, 6.3-V (or 10 V) rated ceramic capacitor to AGND for bypassing of the VCC pin.

Connect a 2.2-µF, 6.3-V (or 10 V) rated ceramic capacitor to PGND for bypassing of the VDRV pin. This bypass

capacitor must refer to PGND pin 7 - 10 to minimize the length of high-frequency driving current path.

Placing a 1-Ω resistor between the VCC and VDRV pin forms a RC filter on VCC pin, which greatly reduces the

noise impact from power stage driver circuit.

8.2.3.5 BOOT Capacitor Selection

Use a minimum of a 0.1-µF capacitor connected from Phase (pin 25) to Boot (pin 26). An optional series boot

resistor of 0 Ω or 2.2 Ω can be added.

8.2.3.6 PG Pullup Resistor Selection

The PG output is an open-drain output and must be pulled up externally through a pullup resistor. Place a pullup

resistor, within a 1-kΩ to 100-kΩ range, at the PG pin (pin 2). In this example, PG is pulled up to VCC/VDRV with

a 10-kΩ resistor.

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TPS548C26

SLVSGM2 – MARCH 2023

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