VOUT UVF

When the FB node voltage (VFB − VGOSNS) drops to 600 mV or lower, the UVF comparator detects and an

internal UVF Response Delay counter begins. When the 16 µs UVF Response Delay expires, the device

responds per the fault response selected through SS pin. With the Latch-off response selected, the device

latches OFF both high-side and low-side FETs. The latch is cleared with a reset of VCC or by toggling the EN

pin. With the Hiccup response selected, the device enters hiccup mode and re-starts automatically after a hiccup

sleep time of 56 ms, without limitation on the number of restart attempts.

The UVF function is enabled only after the soft-start period completes.

During the UVF Response Delay, if the FB node voltage (VFB − VGOSNS) rises above the UVF threshold, thus not

qualified for a UVF event, the UVF response delay timer resets to zero. When the VOUT drops below the UVF

threshold again, the UVF response delay timer re-starts from zero.

VOUT OVF

When the FB node voltage (VFB − VGOSNS) rises to 950 mV or higher, the OVF comparator detects and the

device immediately latches OFF the high-side FET and turns on the low-side FET until the current flowing

through low-side FET exceeds the negative overcurrent (NOC) limit. Upon reaching the −16-A NOC limit, the

low-side FET is turned off, and the high-side FET is turned on again for an on-time determined by PVIN, VOUT,

and fSW setting. The device operates in this cycle until the output voltage is fully discharged. After VOUT is fully

discharged, the high-side FET is latched OFF and the low-side FET is latched ON. With the Latch-off response

selected, the device is kept under the state of the high-side FET latched OFF and the low-side FET latched ON.

The latch is cleared with a reset of VCC or by toggling the EN pin. With the Hiccup response selected, the device

still discharges output voltage by running the NOC operation. However, the device re-starts automatically after a

hiccup sleep time of 56 ms, without limitation on the number of restart attempts. The hiccup sleep time counter

starts right after the OVF trigger.

The OVF function is enabled only after the soft-start period completes.

7.3.14 Overtemperature Protection

To have full coverage for a potential overtemperature event, the TPS548C26 device implements two

overtemperature protection circuitries - one on the Controller side and one on the Power Stage (PS) side.

OTP by Monitoring the Power Stage Temperature

A temperature sensing circuit is implemented in the Power Stage (PS) side. This sensed temperature is fed into

an OTP circuit on the PS side to be compared with a fixed threshold (rising 166°C typical). The device stops the

SW switching when the sensed IC temperature goes beyond the fixed threshold. After the PS die temperature

falls 30°C below the rising threshold, the device automatically restarts with an initiated soft-start. This OTP on

power stage side is a non-latch protection.

OTP by Monitoring the Controller Temperature

The Controller features an internal on-die temperature sensing circuit. The sensed temperature signal is fed

into an OTP comparator on the Controller side and compared with a fixed threshold (rising 166°C typical). The

device stops the SW switching when the sensed Controller temperature goes beyond the fixed threshold. The

device response to an OTP event is set by the SS pin strap detection. With the Latch-off response selected, the

device latches OFF both high-side and low-side FETs. The latch is cleared with a reset of VCC or by toggling

the EN pin. With the Hiccup response selected, the device enters hiccup mode and re-starts automatically after a

hiccup sleep time of 56 ms, without limitation on the number of restart attempts.

Given the power loss on the controller side is much less than the power loss on the power stage side, the OTP

on controller side is unlikely to trigger during the nominal operation.

TPS548C26

SLVSGM2 – MARCH 2023

www.ti.com

18

Submit Document Feedback

Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS548C26