When the internal VCC LDO is used to power the VCC and VDRV pins, the device switching is not gated by

this PVIN UVLO. When the PVIN drops below the level of VDRV UVLO falling threshold plus the LDO dropout

voltage, the VDRV UVLO is triggered and the switching stops. When PVIN rises, the PVIN level has to rise

above the VDRV UVLO rising threshold to enable the switching. This means using the internal VCC LDO does

not allow power conversion under ultra-low PVIN condition.

While, power conversion under ultra-low PVIN condition can be enabled with an external 5-V bias on VCC and

VDRV pins. This configuration allows power conversion under ultra-low PVIN condition down to 2.7 V, as long as

the external bias maintains at a 5-V level to satisfy both the VCC_OK UVLO and the VDRV UVLO.

7.3.2.4 Enable

The TPS548C26 device offers precise enable, disable threshold on the EN pin. The power stage switching is

held off until EN pin voltage rises above the logic high threshold (typically 1.2 V). The power stage switching is

turned off after EN pin voltage drops below the logic low threshold (typically 1 V).

The EN pin has an internal filter to avoid unexpected ON or OFF due to short glitches. The deglitch time is set to

0.2 µs.

The recommended operating condition for EN pin is up to 5.3 V and the absolute maximum rating is 5.5 V. Do

not connect the EN pin to PVIN pin directly.

The TPS548C26 device remains disabled state when EN pin floats. The EN pin is internally pulled down to

AGND through a 125-kΩ resistor.

7.3.3 Set the Output Voltage

The output voltage is programmed by the FB voltage divider resistors, RFB_top and RFB_bot. Connect RFB_top

between the FB pin and the positive node of the load, and connect RFB_bot between the FB pin and GOSNS pin.

The recommended RFB_bot value is 10 kΩ, ranging from 1 kΩ to 20 kΩ. Determine RFB_top by using the below

equation:RFB_top=VOUT−VINTREF

VINTREF −RFB_bot

(1)

Where

• VOUT is the desired output voltage in V.

• VINTREF is 0.8 V.

To achieve the overall VOUT accuracy, using ±1% or better accuracy resistor for the FB voltage divider is highly

recommended.

The output voltage sensed on the VOSNS pin is fed into the internal on-time generation circuitry. TI recommends

shorting the VOSNS pin directly to VOUT sense point (that is, where the RFB_top is connected). Adding any

resistance higher than 51 Ω between VOUT sense point and the VOSNS pin shifts switching frequency higher

than the desired setting. Contact Texas Instruments if a resistor has to be placed between VOUT sense point

and the VOSNS pin.

7.3.4 Differential Remote Sense and Feedback Divider

The TPS548C26 device offers true differential remote sense function which is implemented between FB pin and

GOSNS pin. The output of the differential remote sense amplifier is internally fed into the control loop and does

not come out to a package pin.

Differential remote sense function compensates a potential voltage drop on the PCB traces thus helps maintain

VOUT accuracy under steady state operation and load transient event. Connecting the FB voltage divider

resistors to the remote location allows sensing the output voltage at a remote location. The connections from FB

voltage divider resistors to the remote location must be a pair of PCB traces with at least 12 mil trace width, and

must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher on the sensing location. The

ground connection of the remote sensing signal must be connected to the GOSNS pin. The VOUT connection

of the remote sensing signal must be connected to the VOSNS pin and the top feedback resistor RFB_top. To

maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any

www.ti.com

TPS548C26

SLVSGM2 – MARCH 2023

Copyright © 2023 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: TPS548C26