TPS548C26 datasheet(4/39 Pages) TI

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Table 5-1. Pin Functions (continued)

I/O(1)

DESCRIPTION

NAME

NO.

—

No connection (NC) pin. This pin is floating internally. Pin 37 and pin 6 can be shorted

together.

Power-good output signal. The PG indicator is asserted when the output voltage reaches

the regulation. The PG indicator de-asserts low when the EN pin is pulled low or a

shutdown fault occurs. This open-drain output requires an external pullup resistor.

PGND

7–10, 19

Power ground for the internal power stage.

PHASE

—

Return for high-side MOSFET driver. Shorted to SW internally. Connect the bootstrap

capacitor from BOOT pin to this pin.

PVIN

20–24

Power input for both the power stage. PVIN is the input of the internal VCC LDO as well.

11–18

Output switching terminal of the power converter. Connect these pins to the output

inductor.

VCC

Internal VCC LDO output and also the input for the internal control circuitry. A 2.2 μF (or 1

μF), at least 6.3 V rating ceramic capacitor is required to be placed from VCC pin to AGND

for decoupling.

VDRV

Power supply input for gate driver circuit. A 2.2 μF (or 4.7 μF), at least 6.3 V rating ceramic

capacitor is required to be placed from VDRV pin to PGND pins to decouple the noise

generated by driver circuitry. An external 5 V bias can be connected to this pin to save the

power losses on the internal LDO.

VOSNS

Output voltage sense point for internal on-time generation circuitry. Shorting this pin

directly to VOUT sense point is recommended. Adding any resistance higher than 51 Ω

between VOUT sense point and the VOSNS pin shifts switching frequency higher than the

desired setting. Contact Texas Instruments if a resistor has to be placed between VOUT

sense point and the VOSNS pin.

TPS548C26

SLVSGM2 – MARCH 2023

www.ti.com

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