controller side. Referring the VDRV pin decoupling capacitor to PGND is required to minimize the parasitic loop

inductance for the driver circuitry in the power stage. Placing a 1-Ω resistor between the VCC pin and VDRV pin

forms a RC filter on VCC pin, which greatly reduces the noise impact from power stage driver circuit.

An external bias ranging from 4.75 V to 5.30 V can be connected to the VDRV and VCC pin and power the IC.

This enhances the efficiency of the converter because the VCC and VDRV power supply current now runs off

this external bias instead of the internal linear regulator.

A VDRV UVLO circuit monitors the VDRV pin voltage and disables the switching when the VDRV voltage level

falls below the VDRV UVLO falling threshold. Maintaining a stable and clean VDRV voltage is required for a

smooth operation of the device.

Considerations when using an external bias on the VDRV and VCC pin are shown below:

• Connect the external bias to VDRV pin directly. Place a 1-Ω resistor between the VCC pin and VDRV pin,

then VCC is powered through the 1-Ω filtering resistor.

• For a configuration that the VCC pin and AVIN pin are shorted together, the internal LDO is always forced off.

A valid external bias is required to be connected to VDRV pin (VCC pin and AVIN pin are also powered by the

same external bias through the 1-Ω filtering resistor) so that the internal analog circuits have a stable power

supply rail at their power enable.

• For a configuration that the AVIN pin is not shorted to VCC pin, when the external bias is applied on the

VDRV pin earlier than AVIN rail (VCC pin is also powered by the same external bias through the 1-Ω filtering

resistor), the internal LDO is always forced off and the internal analog circuits have a stable power supply rail

at their power enable.

• The VCC and VDRV pins must be powered by the same source, either the internal VCC LDO, or the same

external bias.

• (Not recommended) When the external bias is applied on the VDRV pin late (for example, after AVIN rail

ramp-up), any power-up and power-down sequencing can be applied as long as there is no excess current

pulled out of the VCC pin. Understand that an external discharge path on the VCC or VDRV pin, which can

pull a current higher than the current limit of the internal LDO, can potentially turn off VCC LDO thereby

shutting off the converter output.

• A good configuration is: Place a 1-Ω resistor between the VCC pin and VDRV pin, and shorting the AVIN pin

to VCC pin.

• A good power-up sequence with above configuration is: The external 5-V bias is applied to VDRV pin first

(VCC pin is also powered by the same external bias through the 1-Ω filtering resistor), then the 12-V bus

applied on PVIN pin, and then the EN signal goes high.

7.3.2 Input Undervoltage Lockout (UVLO)

The TPS548C26 device provides four independent UVLO functions for the broadest range of flexibility in start-up

control. While only the fixed VCC_OK UVLO is required to enable the internal memory initialization, all four

UVLO functions must be met before the switching can be enabled.

7.3.2.1 Fixed VCC_OK UVLO

The TPS548C26 device has an internally fixed UVLO of 3.15 V (typical) on VCC to enable the digital core and

initiate power-on reset, including pin strap detection. The off-threshold on VCC is 3.1 V (typical). After VCC level

rises above 3.15 V (typical) and stays above 3.1 V (typical), the I2C communication is enabled.

7.3.2.2 Fixed VDRV UVLO

The TPS548C26 device has an internally fixed UVLO of 3.6 V (typical) on VDRV to enable drivers for power

FETs and output voltage conversion. The off-threshold on VDRV is 3.4 V (typical).

7.3.2.3 Fixed PVIN UVLO

A PVIN UVLO circuit monitors the PVIN level and turns of switching when PVIN level is insufficient. When

the PVIN pin voltage is lower than the PVINUVLO falling threshold voltage (typically 2.30 V), the device stops

switching and discharges the internal DAC reference. After the PVIN voltage increases beyond the PVINUVLO

rising threshold voltage (typically 2.55 V), the device re-initiates the soft-start and switches again. This PVIN

UVLO is a non-latch protection.

TPS548C26

SLVSGM2 – MARCH 2023

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