Note

The pin strap detection happens at the first stage of power-up sequence. After the detection finishes,

the detection results are latched in and do not change during the following operation. If a new

selection is desired, toggling VCC (or AVIN) is required. Toggling the EN pin does not affect the pin

strap detection results.

7.3.8 Switching Node (SW)

The SW pins connect to the switching node of the power conversion stage. The SW pins act as the return path

for the high-side gate driver. During nominal operation, the voltage swing on SW normally traverses from below

ground to above the input voltage. Parasitic inductance in the PVIN to PGND loop (including the component from

the PCB layout and also the component inside the package) and the output capacitance (COSS) of both power

FETs form a resonant circuit that can produce high frequency (> 100 MHz) ringing on this node. The voltage

peak of this ringing, if not controlled, can be significantly higher than the input voltage. TPS548C26 high-side

gate driver is fine tuned to minimize the peak ringing amplitude so that a RC snubber on SW node is usually not

needed. However, TI highly recommends for the user to measure the voltage stress across either the high-side

or low-side FET and ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit

listed in the Absolute Maximum Ratings table.

7.3.9 Overcurrent Limit and Low-side Current Sense

For a synchronous buck converter, the inductor current increases at a linear rate determined by the input

voltage, the output voltage, and the output inductor value during the high-side MOSFET on-time (ON time).

During the low-side MOSFET on-time (OFF time), this inductor current decreases linearly per slew rate

determined by the output voltage and the output inductor value. The inductor during the OFF time, even with a

negative slew rate, usually flows from the device SW node to the load the device which is said to be sourcing

current and the output current is declared to be positive. This section describes the overcurrent limit feature

based on the positive low-side current. The next section describes the overcurrent limit feature based on the

negative low-side current.

The positive overcurrent limit (OCL) feature in the TPS548C26 device is implemented to clamp low-side valley

current on a cycle-by-cycle basis. The inductor current is monitored during the OFF time by sensing the current

flowing through the low-side MOSFET. When the sensed low-side MOSFET current remains above the selected

OCL threshold, the low-side MOSFET stays ON until the sensed current level becomes lower than the selected

OCL threshold. This operation extends the OFF time and pushes the next ON time (where the high-side

MOSFET turns on) out. As a result, the average output current sourced by the device is reduced. As long as

the load pulls a heavy load where the sensed low-side valley current exceeds the selected OCL threshold, the

device continuously operates in this clamping mode which extends the current OFF time and pushes the next

ON time out. The device does not implement a fault response circuit directly tied to the overcurrent limit circuit,

instead, the VOUT UVF function is used to shuts the device down under an overcurrent fault.

During an overcurrent event, the current sunk by the load (IOUT) exceeds the current sourced by the device

to the output capacitors, thus, the output voltage tends to decrease. Eventually, when the output voltage falls

below the selected undervoltage fault threshold, the VOUT UVF comparator detects and shuts down the device

after the UVF Response Delay (typically 16 µs). The device then responds to the VOUT UVF trigger per fault

response selected through SS pin. With the Latch-off response selected, the device latches OFF both high-side

and low-side drivers. The latch is cleared with a reset of VCC or by toggling the EN pin. With the Hiccup

response selected, the device enters hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms,

without limitation on the number of restart attempts. In other words, the response to an overcurrent fault is set by

the selected UVF response.

If an OCL condition happens during a soft-start ramp the device still operates with the cycle-by-cycle current

limit based on the sensed low-side valley current. This operation can limit the energy charged into the output

capacitors thus the output voltage likely ramps up slower than the desired soft-start slew rate. During the

soft-start, the VOUT UVF comparator is disabled thus the device does not respond to an UVF event. Upon the

completion of the soft-start, the VOUT UVF comparator is enabled, then the device starts responding to the UVF

event.

TPS548C26

SLVSGM2 – MARCH 2023

www.ti.com

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