6.4 Thermal Information

THERMAL METRIC(1)

DEVICE

UNIT

RXX (QFN, JEDEC)

RXX (QFN, TI EVM)

37 PINS

37 PINS

RθJA

Junction-to-ambient thermal resistance

25.4

15.7

°C/W

RθJB

Junction-to-board thermal resistance

3.6

Not applicable(2)

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

6.6

Not applicable(2)

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

3.1

Not applicable(2)

°C/W

ψJT

Junction-to-top characterization parameter

0.1(3)

2.0(4)

°C/W

ψJB

Junction-to-board characterization parameter

3.6

5.7

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

The thermal test or simulation setup is not applicable to a TI EVM layout.

(3)

The power dissipation is evenly distributed across all the silicon areas inside the package on the thermal simulation based on the

JEDEC standard, resulting in the hot spot being centered in the package.

(4)

The power dissipation is concentrated on the power FET area on the thermal simulation based on the TI EVM layout, resulting in the

hot spot being offset inside the package.

6.5 Electrical Characteristics

TJ = –40°C to +125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted). Typical values are at TJ = 25°C,

PVIN = 12 V and VVCC = 4.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

PVIN operating input range

4

16

V

AVIN operating input range

4

16

V

IQ(AVIN)

AVIN quiescent current

Non-switching, PVIN = 12 V, AVIN = 12 V,

VEN = 2 V, VFB = VREF + 50 mV, no bias on

VCC and VDRV pin

5

6.3

7.5

mA

ISD(PVIN)

PVIN shutdown supply current

PVIN = 12 V, AVIN = 12 V, VEN = 0 V, no

bias on VCC and VDRV pin

20

µA

IVCC

VCC and VDRV external bias current

External 5 V bias on VCC and VDRV pin,

regular switching. TJ = 25°C, PVIN = 12 V,

IOUT = 35 A, VEN = 2 V, fSW = 0.6 MHz

32.7

mA

IVCC

VCC and VDRV external bias current

External 5 V bias on VCC and VDRV pin,

regular switching. TJ = 25°C, PVIN = 12 V,

IOUT = 35 A, VEN = 2 V, fSW = 0.8 MHz

39.7

mA

IVCC

VCC and VDRV external bias current

External 5 V bias on VCC and VDRV pin,

regular switching. TJ = 25°C, PVIN = 12 V,

IOUT = 35 A, VEN = 2 V, fSW = 1.0 MHz

48.7

mA

IVCC

VCC and VDRV external bias current

External 5 V bias on VCC and VDRV pin,

regular switching. TJ = 25°C, PVIN = 12 V,

IOUT = 35 A, VEN = 2 V, fSW = 1.2 MHz

57.3

mA

ISD(VCC_VDRV)

VCC + VDRV shutdown supply current

External 5 V bias on VCC and VDRV pin,

PVIN = 12 V, VEN = 0 V

5

6.3

7.5

mA

UVLO

PVINOV

PVIN overvoltage rising threshold

PVIN rising

18.0

18.6

19.2

V

PVINOV

PVIN overvoltage falling threshold

PVIN falling. PVIN_OVF status bit, once it

is set, cannot be cleared unless PVIN falls

below the PVIN overvoltage falling threshold

12.9

13.4

13.9

V

PVINUVLO(R)

PVIN UVLO rising threshold

PVIN rising, external 5 V bias on VCC and

VDRV pin

2.35

2.55

2.75

V

PVINUVLO(F)

PVIN UVLO falling threshold

PVIN falling, external 5 V bias on VCC and

VDRV pin

2.10

2.30

2.50

V

PVINUVLO(H)

PVIN UVLO hysteresis

0.25

V

ENABLE

VEN(R)

EN voltage rising threshold

EN rising, enable switching

1.14

1.19

1.24

V

VEN(F)

EN voltage falling threshold

EN falling, disable switching

0.94

0.98

1.02

V

VEN(H)

EN voltage hysteresis

0.21

V

TPS548C26

SLVSGM2 – MARCH 2023

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