7 Detailed Description

7.1 Overview

The TPS548C26 device is highly integrated buck converter. The device uses D-CAP+ control topology for

fast transient response, and accurate load and line regulation. The device is well-suited for space-constrained

applications such as data center applications, hardware accelerator, server and cloud computing POLs. The

device is easy to use and requires only few external components.

The TPS548C26 has low RDSON and supported external 5-V bias to provide high efficiency up to 35 A of

continuous current operation. the device has true differential remote sense through VOSNS and GOSNS pins,

and an accurate ±1%, with 0.8-V reference over the full operating junction temperature range. The device

uses selectable pin strap internal loop compensation. There is no external compensation required. The device

provides flexibility to select skip-mode or FCCM operation and programmable soft-start time. The device support

overcurrent, overvoltage, undervoltage, and overtemperature protections TPS548C26 is a lead-free device. The

device is fully RoHS compliant without exemption.

7.2 Functional Block Diagram

Low-side current sense

Integration

Loop Compensation

Driver Logic,

Anti-cross-

conduction,

BOOT-SW

UVLO

BOOT switch

Current Sense

gain

VIsns

VCC LDO

Ramp

Generator

BOOT

PVIN

SW

PGND

VDRV

VDRV

Valley current limit

Negative OC

Zero-cross detection

Control logic

Adaptive

On-time

Generator

Isense

+

–

+

PWM

Isense

Vramp

VCOMP

PWM

+

–

FB

GOSNS

VOUT OV/UV

Detection

On-die

Temperature sense

OT Fault

VDIFF

VOSNS

Pin Strap,

Housekeeping,

and

Memory

VCC

AGND

DVDD LDO

AGND

NC 33

EN_PWM

EN_PWM

EN

NC 34

NC 35

SS

ILIM

MODE

PG

VCC

DNC

NC

VDRV

AVIN

PHASE

OVF/UVF

OVF/UVF

PG

7.3 Feature Description

7.3.1 Internal VCC LDO and Using an External Bias on VCC and VDRV Pin

The TPS548C26 device has an internal 4.5-V LDO featuring input from the AVIN pin and output to the VCC pin.

When the AVIN voltage rises, the internal LDO is enabled automatically and starts regulating the LDO output

voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry on the

controller side, and the VDRV voltage provides the supply voltage for the power stage side.

Either the VCC or VDRV pin must be bypassed with a 2.2 μF, at least 6.3-V rating ceramic capacitor. Connecting

the VCC pin decoupling capacitor to AGND is required to provide a clean ground for the analog circuitry on the

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TPS548C26

SLVSGM2 – MARCH 2023

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