DRV8461SPWPR datasheet(23/117 Pages) TI

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Table 7-9. Non-Circular 1/2-Stepping Current (continued)

NON-CIRCULAR 1/2-STEP

AOUT CURRENT

(% FULL-SCALE)

BOUT CURRENT

(% FULL-SCALE)

ELECTRICAL ANGLE

(DEGREES)

–100

100

315

When operating with the SPI, depending on the STEP_EDGE bit, STEP active edge can be either rising edge

or both rising and falling edge, as shown in Table 7-10. When configured with H/W interface, the STEP active

edge is only the rising edge. For applications that need to run at high input STEP rate, configuring both edges as

active edge reduces controller overhead by half, because the input STEP rate is effectively doubled.

Table 7-10. STEP Active Edge

Interface

STEP_EDGE

STEP Active Edge

SPI

0b (default)

Rising edge

Rising edge and falling edge

H/W

Rising edge

At each active edge of the STEP input the indexer advances to the next state in the table. The direction shown

is with the DIR pin logic high. If the DIR pin is logic low, the sequence table is reversed. If the step mode is

changed dynamically while stepping, the indexer advances to the next valid state for the new step mode setting

at the active edge of STEP.

After power-up, after exiting logic undervoltage lockout, or after exiting sleep mode, the indexer moves to an

initial excitation state (home position) of 45° electrical angle, corresponding to 71% of full-scale current in both

coils. All the registers are restored to their deafult values in such scenario.

When operating with the SPI, if the IDX_RST bit is 1b, it resets the indexer to 45° electrical angle as shown in

Figure 7-5, but the contents of the memory map registers do not change.

Traces from top to bottom: AOUT2, AOUT1, STEP, coil B current, coil A current, nSCS

Figure 7-5. Indexer reset

If the STEP input frequency is jittery, the device filters the signal for the purpose of stall detection. The

FRQ_CHG and STEP_FRQ_TOL bits program the filter setting, as shown in Table 7-11. 2% filtering means

up to 2% jitter around the center frequency will be filtered out to generate a clean STEP signal for internal

circuits to detect motor stall.

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DRV8461

SLOSE98 – DECEMBER 2022

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