DRV8461SPWPR datasheet(55/117 Pages) TI

55 / 117 page

7.3.19 Protection Circuits

The device is fully protected against supply undervoltage, charge pump undervoltage, output overcurrent, open

load, and device overtemperature events. In addition, when operating with SPI interface, the device is protected

against stall detection in the event of overload or end-of-line movement.

7.3.19.1 VM Undervoltage Lockout

If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage:

• All the outputs are disabled (High-Z)

• The charge pump is disabled

• nFAULT is driven low

Normal operation resumes (motor driver and charge pump) when the VM voltage recovers above the UVLO

rising threshold voltage.

When operating with SPI interface, if the voltage on the VM pin falls below the UVLO falling threshold voltage,

but is above the VRST or VCC UVLO (shown in Figure 7-39) :

• SPI communication is available and the digital core of the device is active

• The FAULT and UVLO bits are made 1b

• The nFAULT pin is driven low

From this condition, if the VM voltage recovers above the UVLO rising threshold voltage:

• nFAULT pin is released (is pulled-up to the external voltage)

• The FAULT bit becomes 0b

• The UVLO bit remains latched 1b until cleared through the CLR_FLT bit or an nSLEEP reset pulse.

VRST UVLO reset

or VCC UVLO

VUVLO rising

VUVLO falling

Device Status

SPI available

Digital Alive

Outputs switching

CP enabled

UVLO, FAULT bits 0b*

nFAULT high

Time

VM Voltage

* FAULT bit will be 0b if no fault is present

** UVLO bit will be 1b till cleared by CLR_FLT or nSLEEP pulse

SPI available

Digital Alive

Outputs switching

CP enabled

UVLO bit 1b**

FAULT bit 0b*

nFAULT high

SPI available

Digital Alive

Outputs Hi-Z

CP disabled

UVLO, FAULT bits 1b

nFAULT low

Figure 7-39. Supply Voltage Ramp Profile

When the voltage on the VM pin falls below the VRST or VCC UVLO (shown in Figure 7-40) :

• SPI communication is unavailable and the digital core is shutdown

• The FAULT and UVLO bits are 0b

• The nFAULT pin is high

During a subsequent power-up, when the VM voltage exceeds the VRST voltage:

• The digital core comes alive

• UVLO bit stays at 0b

• The FAULT bit is made 1b

• The nFAULT pin is pulled low

• When the VM voltage exceeds the VM UVLO rising threshold

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DRV8461

SLOSE98 – DECEMBER 2022

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