L9960 datasheet(14/95 Pages) STMICROELECTRONICS

14 / 95 page

General electrical characteristics

L9960, L9960T

14/95

DS11115 Rev 10

General electrical characteristics

3.1

Absolute maximum ratings

Warning:

Warning: stressing the device above the rating listed in the

“Absolute maximum ratings” table may cause permanent

damage to the device. These are stress ratings only and

operation of the device at these or any other conditions

above those indicated in the operating sections of this

specification is not implied. Exposure to the absolute

maximum ratings conditions for extended periods may affect

the device reliability.

Note:

Test circuit according to HBM (EIA/JESD22-A114-B) and CDM (EIA/JESD22-C101-C).

Table 4. Absolute maximum ratings

Symbol

Parameter

Condition

Min

Max

Unit

Vps

Supply voltage

Continuous

-1

Vout1,2

Output voltage

Continuous. OUT is limited by VPS

-1

VDD5

Logic supply voltage

0 V < Vps < 40 V

-0.3

VDDIO

SDO supply voltage

0V<Vps<40V

-0.3

VCP

VCP output voltage

-0.3

Vps+5

VIN

Logic input voltage (NCS, SDI, SCLK,

DIR, PWM, DIS, NDIS)

0V<Vps <40V

0V<VDD5 <19 V

-0.3

Logic output voltage (SDO, NDIS)

-0.3

Human body model ESD compliance

for pins: OUTx,VPS (not tested at

ATE)(1)

HBM (100 pF/1.5 kohm)

-4

Human body model ESD compliance

for other pins than OUTx, VPS (not

tested at ATE)

HBM (100 pF/1.5 kohm)

-2

Charge Device Model ESD compliance

for all pins (not tested at ATE)

CDM; according to Q100-011

classification C3B

-750

-500

750(2)

500(3)

ISO 7637 pulses

Cf. standards

Latch-up immunity

According to JEDEC 78 class 2 level A

1. Versus GND.

2. Corner pins.

3. All pins.

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