L9960 datasheet(74/95 Pages) STMICROELECTRONICS

74 / 95 page

Functional description

L9960, L9960T

74/95

DS11115 Rev 10

4.9.1

Protocol description

Transfer format uses 16 bits word in case of single device configuration and multiple of 16

bits word in case of daisy chain configuration (number of devices in the daisy chain is not

limited).

A command sent by the µcontroller during transfer N is answered during transfer N+1.

Figure 33. SPI SDO update at 2nd SPI command

SDO is clocked on SCLK rising edge.

Figure 34. SPI SDO is clocked on SCLK rising edge

SDI is sampled on falling edge.

When NCS = '1' and during Reset, any signals at the SCLK and SDI pins have to be

ignored, and SDO remains in a high impedance state. Otherwise, the SPI interface is

always active.

SCLK is guaranteed to be at '0' when NCS rises and falls (guaranteed by application).

At each rising edge of the clock pulse after NCS goes low, the response word is serially

shifted out on the SDO pin.

At each falling edge of the clock pulse (after NCS goes low) the new control word is serially

shifted in on the SDI pin. The SPI command bits are decoded to determine the destination

address for the data bits. After the 16th (or multiple of 16, for daisy chains) clock cycle, at

the next NCS low to high transition, the SPI shift register data bits are transferred into the

latch whose address was decoded from the SPI shift register command bits.

A command is executed after 16 SCLK cycles (or a multiple of 16) and NCS goes high.

In case of "no SCLK edge" when NCS = '0', the transfer is considered as valid: no error is

returned to the µcontroller. The answer of last command is sent during next transfer.

Figure 35. In case of no SCLK edge when NCS=0

Command N

Command N+1

NCS

SDI

SDO

Answer to cmd N

Answer to cmd N -1

GAPGPS02363

MSB

SCLK

NCS

LSB

...

SDO

GAPGPS02364

Command N

Command N+1

NCS

SCLK

SDO

Answer to cmd N

Answer to cmd N -1

GAPGPS02365

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