VSC8658 datasheet(86/95 Pages) MICROSEMI

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Pin Descriptions

VMDS-10242 VSC8658 Datasheet Revision 4.1

7.2.6

JTAG

The following table lists the pins associated with the device JTAG testing facility.

7.2.7

Power Supply

The following table lists the device power supply pins.

EEDAT

IPD/O

(Optional) EEPROM serial I/O data. Used to configure

PHYs in a system without a Station Manager. Connect to

the SDA pin of the ATMEL “AT24CXXX” serial EEPROM

device family.

The VSC8658 device determines that an external

EEPROM is present by monitoring the EEDAT pin at

power-up or when NRESET is de-asserted. If EEDAT has

a 4.7 k

Ω external pull-up resistor, the VSC8658 assumes

an EEPROM is present. The EEDAT pin can be left

floating or grounded to indicate no EEPROM.

EECLK

(Optional) EEPROM serial output clock. Used to configure

PHYs in a system without a station manager. Connect to

the SCL pin of the ATMEL “AT24CXXX” serial EEPROM

device family.

AA3

NRESET

IPU

Device reset. Active low input that powers down the

device and sets the register bits to their default state.

CLKOUT

Clock output can be enabled or disabled and also output

a reference clock frequency of 125 MHz or 156.25 MHz

using CMODE or register setting. This pin is not active

when NRESET is asserted. When disabled, the pin is held

low.

Table 87 •

JTAG Pins

Name

Type

Description

TDI

IPU5V

JTAG test serial data input.

TDO

JTAG test serial data output.

TMS

IPU5V

JTAG test mode select.

TCK

IPU5V

JTAG test clock input.

NTRST

IPU5V

JTAG reset. If JTAG is not used, then tie this pin to VSS

(ground) with a pull-down resistor.

Table 88 •

Power Supply Pins

Name

Type

Description

C3 C4 C10 C11 C12 C16 C17 C21 C23

C25 D3 D4 D10 D11 D12 D16 D17 D21

D22 F24 G23 H23 H24 J23 M23 M24

N1 N2 N3 N4 R25 R26 U4 AA23 AB23

AD3 AD5 AD7 AD11 AD12 AD14 AD17

AD20 AD21

VDD33

3.3 V

General 3.3 V power supply

Table 86 •

SMI Pins (continued)

Name

Type

Description

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