VSC8658 datasheet(24/95 Pages) MICROSEMI

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Functional Descriptions

VMDS-10242 VSC8658 Datasheet Revision 4.1

•CLKOUT

In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low

power state and transitions to the normal operating state when signal energy is detected on the media.

This happens when the PHY is connected to one of the following:

•

Auto-negotiation capable link partner

•

Another PHY in enhanced ActiPHY LP wake-up state

In the absence of signal energy on the media pins, the PHY transitions from the low power state to the

LP wake-up state periodically based on the programmable sleep timer (register bits 20E.14:13). The

actual sleep time duration is randomized from –80 milliseconds (ms) to +60 ms to avoid two linked PHYs

in ActiPHY mode entering a lock-up state during operation.

4.12.2

Link Partner Wake-up State

In this state, the PHY attempts to wake up the link partner. Up to three complete FLP bursts are sent on

alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer, which is set using

In this state, the following functionality is provided:

•

SMI interface (MDC, MDIO, MDINT_n)

•CLKOUT

After sending signal energy on the relevant media, the PHY returns to the low power state.

4.12.3

Normal Operating State

In this state, the PHY establishes a link with a link partner. When the media is unplugged or the link

partner is powered down, the PHY waits for the duration of the programmable link status time-out timer,

which is set using register bit 28.7 and bit 28.2. It then enters the low power state.

4.13

Serial Management Interface

The VSC8658 device includes an IEEE 802.3-compliant serial management interface (SMI) that is

affected by use of its MDC and MDIO pins. The SMI provides access to device control and status

registers. The register set that controls the SMI consists of 32 16-bit registers, including all required

IEEE-specified registers. Also, there are additional pages of registers accessible using device register

31.

For more information, see Extended Page Registers, page 45.

The SMI is a synchronous serial interface with bidirectional data on the MDIO pin that is clocked on the

rising edge of the MDC pin. The interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending

on the total load on MDIO. An external, 2 k

Ω pull-up resistor is required on the MDIO pin.

4.13.1

SMI Frames

Data is transferred over the SMI using 32-bit frames with an optional and arbitrary length preamble. The

following illustrations show the SMI frame format for the read operation and write operation.

Figure 9 •

SMI Read Frame

MDC

MDIO

Preamble

(optional)

SFD

Read

PHY Address

to PHY

D15 D14 D13 D12 D11 D10 D9

Idle

Station Manager Drives MDIO

PHY Drives MDIO

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