VSC8658 datasheet(53/95 Pages) MICROSEMI

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Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

Note: Bits 29.11:10 are controlled only by port 0 and affect the behavior of all ports.

5.3

Extended Page Registers

To provide functionality beyond the IEEE802.3-specified 32 registers and main device registers, the

VSC8658 device includes an extended set of registers that provide an additional 15 register spaces.

To access the extended page registers (16E through 30E), enable extended register access by writing

0x0001 to register 31. For more information, see Table 37, page 46.

When extended page register access is enabled, reads and writes to registers 16 through 30 affect the

extended registers 16E through 30E instead of those same registers in the IEEE-specified register

space. Registers 0 through 15 are not affected by the state of the extended page register access.

Writing 0x0000 to register 31 restores the main register access.

The following table lists the addresses and register names in the extended register page space. These

registers are accessible only when the device register 31 is set to 0x0001.

LED3 combine

feature disable

R/W

This is a sticky bit.

0 = Combine enabled (link/activity,

duplex/collision).

1 = Disable combination (link only,

duplex only).

CMODE

LED2 combine

feature disable

R/W

This is a sticky bit.

0 = Combine enabled (link/activity,

duplex/collision).

1 = Disable combination (link only,

duplex only).

CMODE

LED1 combine

feature disable

R/W

This is a sticky bit.

0 = Combine enabled (link/activity,

duplex/collision).

1 = Disable combination (link only,

duplex only).

CMODE

LED0 combine

feature disable

R/W

This is a sticky bit.

0 = Combine enabled (link/activity,

duplex/collision).

1 = Disable combination (link only,

duplex only).

CMODE

Table 36 •

Extended Registers Page Space

16E

SerDes Media control

17E

SerDes MAC/Media control

18E

CRC good counter

19E

SIGDET polarity control

20E

Extended PHY control 3 (ActiPHY)

21E

EEPROM interface status and control

22E

EEPROM data read or write

23E

Extended PHY control 4 (PoE and CRC error counter)

24E

VeriPHY 1

Table 35 •

LED Behavior, Address 30 (0x1E) (continued)

Bit

Name

Access

Description

Default

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