VSC8658 datasheet(44/95 Pages) MICROSEMI

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Configuration

VMDS-10242 VSC8658 Datasheet Revision 4.1

Note If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is

returned to the user through the SMI after the base page is exchanged. The user then must send the

correct sequence of next pages to the link partner, determine the common capabilities, and force the

device into the correct configuration following the successful exchange of pages.

5.2.16

Reserved Main Address Space

The bits in register 19, register 20, and register 21 (0x13, 0x14, and 0x15, respectively) are reserved.

5.2.17

Extended Control and Status

The bits in register 22 provide additional device control and readouts. The following table shows the

settings available.

Disable polarity

correction

R/W

This is a sticky bit.

1 = Disable polarity inversion correction on

each subchannel.

Parallel detect control R/W

This is a sticky bit.

1 = Do not ignore advertised ability.

0 = Ignore advertised ability.

2Reserved

Disable automatic

1000BASE-T next

page exchange

R/W

This is a sticky bit.

1 = Disable automatic 1000BASE-T next page

exchanges.

CLKOUT output

enable

R/W

This is a sticky bit.

1 = Enable clock output pin.

CMODE

Table 26 •

Extended Control and Status, Address 22 (0x16)

Bit

Name

Access

Description

Default

Force 10BASE-T

link high

R/W

This is a sticky bit.

1 = Bypass link integrity test.

0 = Enable link integrity test.

Jabber detect

disable

R/W

This is a sticky bit.

1 = Disable jabber detect.

Disable 10BASE-T

echo

R/W

This is a sticky bit.

1 = Disable 10BASE-T echo.

Reserved

11:10

10BASE-T squelch

control

R/W

This is a sticky bit.

00 = Normal squelch.

01 = Low squelch.

10 = High squelch.

11 = Reserved.

Sticky reset enable R/W

This is a super-sticky bit.

1 = Enabled.

EOF Error

This bit is self-clearing.

1 = EOF error detected.

10BASE-T

disconnect state

This bit is self-clearing.

1 = 10BASE-T link disconnect detected.

Table 25 •

Bypass Control, Address 18 (0x12) (continued)

Bit

Name

Access

Description

Default

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