VSC8658 datasheet(29/95 Pages) MICROSEMI

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Functional Descriptions

VMDS-10242 VSC8658 Datasheet Revision 4.1

4.15

GPIO Pins

The VSC8658 provides up to 8 dedicated general-purpose input/output (GPIO) pins. In addition, the

eight device SIGDET pins can also be configured as eight GPIO pins, resulting in a total of 16 GPIO pins.

All device GPIO pins and their behavior are controlled using registers. For more information, see

General-Purpose I/O Registers, page 52.

4.16

Testing Features

The VSC8658 device includes several testing features designed to make it easier to perform system-

level debugging and in-system production testing. This section describes the available features.

4.16.1

Ethernet Packet Generator (EPG)

The device EPG can be used at each of the 10/100/1000BASE-T speed settings for Copper Cat5 media

to isolate problems between the MAC and the VSC8658 device, or between a locally connected PHY

and its remote link partner. Enabling the EPG feature effectively disables all MAC interface transmit pins

and selects the EPG as the source for all data transmitted onto the twisted pair interface.

Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use

the EPG testing feature when the VSC8658 device is connected to a live network.

To enable the VSC8658 device EPG feature, set the device register bit 29E.15 to 1.

When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY.

However, the PHY receive output pins to the MAC are still active when the EPG is enabled. If it is

necessary to disable the MAC receive pins as well, set the register bit 0.10 to 1.

When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet packets based on

the settings in registers 29E and 30E. These registers set:

•

Source and destination addresses for each packet

•

Packet size

•

Inter-packet gap

•

FCS state

•

Transmit duration

•

Payload pattern

If register bit 29E.13 is set to 0, register bit 29E.14 is cleared automatically after 30,000,000 packets are

transmitted.

4.16.2

CRC Counters

Two separate cyclical redundancy checking (CRC) counters are available on all PHYs in the VSC8658

device. There is a 14-bit good CRC counter available in register bits 18E.13:0 and a separate 8-bit

counter available in register bits 23E.7:0.

The device CRC counters operate in the 100BASE-FX/1000BASE-X over SerDes mode as well as in the

10/100/1000BASE-T mode testing as follows:

Bit 9.

Reserved

Bit 21.

Reserved

Bit 33.

Reserved

Bit 45.

Reserved

Bit 57.

Reserved

Bit 69.

Reserved

Bit 81.

Reserved

Bit 93.

Reserved

Bit 10. TX

Activity

Bit 22. TX

Activity

Bit 34. TX

Activity

Bit 46. TX

Activity

Bit 58. TX

Activity

Bit 70. TX

Activity

Bit 82. TX

Activity

Bit 94. TX

Activity

Bit 11. RX

Activity

Bit 23. RX

Activity

Bit 35. RX

Activity

Bit 47. RX

Activity

Bit 59. RX

Activity

Bit 71. RX

Activity

Bit 83. RX

Activity

Bit 95. RX

Activity

Bit 12. Auto-

Negotiation

Fault

Bit 24. Auto-

Negotiation

Fault

Bit 36. Auto-

Negotiation

Fault

Bit 48. Auto-

Negotiation

Fault

Bit 60. Auto-

Negotiation

Fault

Bit 72. Auto-

Negotiation

Fault

Bit 84. Auto-

Negotiation

Fault

Bit 96. Auto-

Negotiation

Fault

Table 6 •

LED Serial Stream Order (continued)

PHY0

PHY1

PHY2

PHY3

PHY4

PHY5

PHY6

PHY7

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