UPD360 datasheet(191/221 Pages) MICROCHIP

191 / 221 page

 2016-2017 Microchip Technology Inc.

DS00002084C-page 191

UPD360

50uS later, FET C is shorted. The voltage at the input of the core regulator is 3V3_VBUS.

13.2

Software Override

In the event that both 3V3_VBUS and 3V3_ALW are available, the Power Switch automatically selects 3V3_ALW for

operation. This can be overridden by the VBUS Switch Enable Override (VBUS_SW_EN_OVR) bit of the Power Switch

Control Register (PWR_SW_CTL), which forces the switch to operate off of VBUS. When this bit is set, the auto-switch

mechanism of the switch is disabled.

13.3

Power Switch Interrupts

The power switch interrupt alerts software to changes in the state of the Power Switch. These events are listed in the

Power Switch Interrupt Status Register (PWR_INT_STS). The interrupt persists until the asserted bits in the Power

Switch Interrupt Status Register (PWR_INT_STS) are cleared. Individual interrupt events can be a enabled via the

Power Switch Interrupt Enable Register (PWR_INT_EN). Power switch interrupt status sources are capable of triggering

asynchronous wakes.

13.4

Power Switch Registers

This section details the power switch registers. For an overview of the entire device register map, refer to Section 4.0,

"Register Map," on page 19.

FIGURE 13-16:

POWER SWITCH: VBUS PRESENT, 3V3_ALW GOING AWAY STEP FIVE

TABLE 13-1:

POWER SWITCH REGISTER MAP

Address

1C00h

Power Switch Control Register (PWR_SW_CTL)

1C01h

Power Switch Status Register (PWR_SW_STS)

1C02h

Power Switch Interrupt Status Register (PWR_INT_STS)

1C03h

Power Switch Interrupt Enable Register (PWR_INT_EN)

1C04h

Power Switch State Status Register (PWR_SW_STATE_STS)

1C05h – 1FFFh

Reserved for future expansion

3V3_ALW

3V3_ VBUS

VSW

3V3_VBUS_PWRGD=1

3V3_ALWAYS_PWRGD=0

3V3_VBUS

LDOs

VCORE _PWRGD

1.8V Analog

1.8V Core

VMUX_PWRGD

SWITCH

CONTROL

3V3_ALWAYS_PWRGD

3V3_VBUS_PWRGD

VCORE_PWRGD

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