FXPS7115D4 datasheet(52/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

52 / 72

Table 95. ASICWFR_Y Register (address CDh) bit allocation

Bit

Symbol

ASICWFR_Y[7:0]

Reset

N/A

Access

Table 96. ASICWLOT_L Register (address D0h) bit allocation

Bit

Symbol

ASICWLOT_L[7:0]

Reset

N/A

Access

Table 97. ASICWLOT_H Register (address D1h) bit allocation

Bit

Symbol

ASICWLOT_H[7:0]

Reset

N/A

Access

7.7.30 USERDATA_0 to USERDATA_E - user data registers

User data registers are user programmable OTP registers that contain user-specific

information. These registers are included in the user programmed OTP array error

detection. These registers are readable and writable in SPI mode or I2C mode when

ENDINIT is not set.

7.7.31 USERDATA_10 to USERDATA_1E - user data registers

User data registers are user programmable OTP registers that contain user-specific

information. These registers are included in the user programmed OTP array error

detection. These registers are readable and writable in SPI mode or I2C mode when

ENDINIT is not set.

7.7.32 Lock and CRC Registers

The lock and CRC Registers are automatically programmed OTP registers that include

the lock bit, the block identifier, and the block OTP array CRC use for error detection.

These registers are automatically programmed when the corresponding data array is

programmed to OTP using the Write OTP Enable register.

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