FXPS7115D4 datasheet(14/72 Pages) NXP

14 / 72 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

14 / 72

7.4.1 I2C bit transmissions

The state of SDA when SCL is high determines the bit value being transmitted. SDA

must be stable when SCL is high and change when SCL is low as shown in Figure 14.

After the START signal has been transmitted by the master, the bus is considered busy.

Timing for the start condition is specified in Table 102.

aaa-029746

SDA

SDA stable

SDA = `1'

SDA stable

SDA = `0'

SDA

changes

SCL

Figure 14. I2C bit transmissions

7.4.2 I2C start condition

A bus operation is always started with a start condition (START) from the master.

A START is defined as a high to low transition on SDA while SCL is high as shown

in Figure 15. After the START signal has been transmitted by the master, the bus is

considered busy. Timing for the start condition is specified in Table 102.

A start condition (START) and a repeat START condition (rSTART) are identical.

aaa-029747

SDA

SCL

START

Figure 15. I2C start condition

7.4.3 I2C byte transmission

Data transfers are completed in byte increments. The number of bytes that can be

transmitted per transfer is unrestricted. Each byte must be followed by an acknowledge

bit (Section 7.4.4 "I2C acknowledge and not acknowledge transmissions") from the

receiver. Data is transferred with the most significant bit (MSB) first (see Figure 16).

The master generates all clock pulses, including the ninth clock for the acknowledge bit.

Timing for the byte transmissions is specified in Section 7.4.4 "I2C acknowledge and

not acknowledge transmissions". All functions for this device are completed within the

acknowledge clock pulse. Clock stretching is not used.

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