FXPS7115D4 datasheet(27/72 Pages) NXP

27 / 72 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

FXPS7115D4

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Product data sheet

Rev. 3 — 5 December 2019

27 / 72

7.5.5.4 SPI data output verification error

The device includes a function to verify the integrity of the data output to the MISO pin.

The function compares the data transmitted on the MISO pin to the data intended to be

transmitted. If any one bit does not match, a SPI MISO mismatch fault is detected and

the MISO_ERR flag in the DEVSTAT2 register is set.

If a valid sensor data request message is received during the SPI transfer with the MISO

mismatch failure, the request is ignored and the device responds with the error response

as described in Section 7.5.5.2 "Error responses" with the detailed status field set to

“SPI Error” as defined in Section 7.5.5.1 "Basic status field" during the subsequent SPI

message.

If a valid register write request message is received during the SPI transfer with the

MISO mismatch failure, the register write is completed as requested, but the device

responds with the error response as described in Section 7.5.5.2 "Error responses" with

the detailed status field set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field"

during the subsequent SPI message.

If a valid register read request message is received during the SPI transfer with the MISO

mismatch failure, the register read is ignored and the device responds with the error

response as described in Section 7.5.5.2 "Error responses" with the detailed status field

set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field", during the subsequent

SPI message.

aaa-023748

D Q

MISO ERR

SCLK

MISO

DATA OUT BUFFER

SPI DATA OUT SHIFT REGISTER

D Q

Figure 21. SPI data output verification

7.5.6 SPI timing diagram

aaa-023749

DSP Out

SS_B

SCLK

MISO

MOSI

tDISABLE

tCLKSS

tLAT

tSSN

tSSCLK

tSCLKH

tSCLKF

tSCLKR

tSCLK

tLEAD

tLAG

tHOLD_IN

tHOLD_OUT

tVALID

tSCLKL

tACCESS

tSETUP

Figure 22. SPI timing diagram

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