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FXPS7115D4 датащи(PDF) 50 Page - NXP Semiconductors |
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FXPS7115D4 датащи(HTML) 50 Page - NXP Semiconductors |
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50 / 72 page ![]() NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa FXPS7115D4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 3 — 5 December 2019 50 / 72 7.7.26 IC manufacturer identification register (address C2h) The IC manufacturer identification register is a factory programmable OTP register that identifies NXP as the IC manufacturer. This register is included in the factory programmed OTP array error detection. This register is readable in SPI mode or I2C mode when ENDINIT is not set. Table 85. IC MANUFACTURER IDENTIFICATION REGISTER (ICMFGID address C2h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ICMFGID[7:0] Reset 0 0 0 0 0 0 1 0 Access R R R R R R R R 7.7.27 Part number register (address C4h, C5h) The part number registers are factory programmed OTP registers that include the numeric portion of the device part number. These registers are included in the factory programmed OTP array error detection. These registers are readable in SPI mode or I2C mode when ENDINIT is not set. Table 86. PN0 Register (address C4h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PN0[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 87. PN1 Register (address C5h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PN1[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R 7.7.28 Device serial number registers The serial number registers are factory programmed OTP registers that include the unique serial number of the device. Serial numbers begin at 1 for all produced devices in each lot and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 14-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial numbers might not be assigned. These registers are included in the factory programmed OTP array error detection. These registers are readable in SPI mode or I2C mode when ENDINIT is not set. Table 88. SN0 Register (address C6h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SN[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R |
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