FXPS7115D4 datasheet(34/72 Pages) NXP

34 / 72 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

FXPS7115D4

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Product data sheet

Rev. 3 — 5 December 2019

34 / 72

Table 39. DEVSTAT2 - device status register (address 03h) bit description

Bit

Symbol

Description

F_OTP_ERR

The NXP factory OTP array error bit is set if a fault is detected in the factory OTP array.

This error is cleared by a read of the DEVSTAT2 register through any communication

interface or on a data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the NXP factory OTP array

U_OTP_ERR

The user OTP array error bit is set if a fault is detected in the user OTP array. This error is

cleared by a read of the DEVSTAT2 register through any communication interface or on a

data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the user OTP array

U_RW_ERR

When ENDINIT is set, an error detection is enabled for all user writable registers. The

error detection code is continuously calculated on the user writable registers and verified

against a previously calculated error detection code. If a mismatch is detected in the error

detection, the U_RW_ERR bit is set. This error is cleared by a read of the DEVSTAT2

error in the status field.

0 — No error detected

1 — Error detected in the user read/write array

U_W_ACTIVE

The user OTP write in process status bit is set if a user initiated write to OTP is currently

in process. The U_W_ACTIVE bit is automatically cleared once the write to OTP is

complete.

0 — No OTP write in process

1 — OTP write in process

TEMP0_ERR

The temperature error bit is set if an overtemperature or undertemperature condition

exists. This error is cleared by a read of the DEVSTAT2 register through any

communication interface or on a data transmission that includes the error in the status

field.

0 — No error detected

1 — Overtemperature or undertemperature error condition detected

7.7.2.4 DEVSTAT3 - device status register (address 04h)

Table 40. DEVSTAT3 - device status register (address 04h) bit allocation

Bit

Symbol MISO_ERR OSCTRAIN_

ERR

reserved

Reset

reserved

Access

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