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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FXPS7115D4 датащи(PDF) 48 Page - NXP Semiconductors |
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FXPS7115D4 датащи(HTML) 48 Page - NXP Semiconductors |
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48 / 72 page  NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa FXPS7115D4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 3 — 5 December 2019 48 / 72 Table 79. SNSDATA0_TIMEx - time stamp register (address 66h to 6Bh) bit allocation Location Bit Address Symbol 7 6 5 4 3 2 1 0 66h SNSDATA0_TIME0 SNSDATA0_TIME[7:0] 67h SNSDATA0_TIME1 SNSDATA0_TIME[15:8] 68h SNSDATA0_TIME2 SNSDATA0_TIME[23:16] 69h SNSDATA0_TIME3 SNSDATA0_TIME[31:24] 6Ah SNSDATA0_TIME4 SNSDATA0_TIME[39:32] 6Bh SNSDATA0_TIME5 SNSDATA0_TIME[47:40] Factory default 0 0 0 0 0 0 0 0 Access R R R R R R R R 7.7.21 P_MAX, P_MIN - maximum and minimum absolute pressure value registers (address 6Ch to 6Fh) The minimum and maximum absolute pressure value registers are read-only registers that contain a sample-by-sample continuously updated minimum and maximum 16- bit absolute pressure value. The value is reset to 0000h on a write to a DSP_CFG_U1 register that changes the value of the LPF[2:0] or ST_CTRL[3:0]. These registers are readable in SPI mode or I2C mode. In I2C mode the P_xxx_H register value is latched on a read of the P_xxx_L register value until the P_xxx_H register is read. To avoid data mismatch, the user is required to always read the registers in sequence, P_xxx_L register first, followed by the P_xxx_H register. Table 80. P_Max and P_Min registers (address 6Ch to 6Fh) bit allocation Location Bit Address Symbol 7 6 5 4 3 2 1 0 6Ch P_MAX_L P_MAX[7:0] 6Dh P_MAX_H P_MAX[15:8] 6Eh P_MIN_L P_MIN[7:0] 6Fh P_MIN_H P_MIN[15:8] Factory default 0 0 0 0 0 0 0 0 Access R R R R R R R R 7.7.22 FRT - free running timer registers (addresses 78h to 7Dh) The free running timer registers are read-only registers that contain a 48-bit free running timer. The free running timer is clocked by the main oscillator frequency and increments every 100 ns. Table 81. FRT - free running timer registers (addresses 78h to 7Dh) bit allocation Location Bit Address Symbol 7 6 5 4 3 2 1 0 78h FRT0 FRT[7:0] 79h FRT1 FRT[15:8] 7Ah FRT2 FRT[23:16] 7Bh FRT3 FRT[31:24] 7Ch FRT4 FRT[39:32] 7Dh FRT5 FRT[47:40] Access R R R R R R R R |
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