CS7620 datasheet(42/70 Pages) CIRRUS

42 / 70 page

CS7620

DS301PP2

4.21

Timing Control - Start of Active Pixels

Default = 4Bh; Read/Write (address 1Fh)

4.22

Timing Control - Vertical Time Division

Default = 01h; Read/Write (address 20h)

Bit Number

765432

Bit Name

act_begin7

act_begin6

act_begin5

act_begin4

act_begin3

act_begin2

act_begin1

act_begin0

Default

1001011

Bit

Mnemonic

Function

act_begin7

Active Pixels: This register should be programmed with the pixel number of

the first active pixel to be read out. That is the first pixel after the extra pixels,

the black pixels, and the grey pixel.

This register value is used by the CS7620 when the part is in the valid data

mode to generate the data valid signal on the CLKO pin.

Valid data can be set through the above mentioned registers together with

act_begin(1Fh) to define a subset of pixels to be passed to the subsequent

ASIC or DSP component. This subset may or may not include dark rows

and/or dark pixels. Please refer to Figure 28.

The default value is set to 75, which is the sum of the blk_end register (1Dh)

and act_rws_lst register (1Eh).

act_begin6

act_begin5

act_begin4

act_begin3

act_begin2

act_begin1

act_begin0

Bit Number

765432

Bit Name

Reserved

tdv4

tdv3

tdv2

tdv1

tdv0

Default

---

00001

Bit

Mnemonic

Function

7:5

Reserved

4tdv4

Critical Timing: This determines the width of the minimum vertical division

measured in pixel clocks. (One vertical pixel shift (row) requires 8 vertical time

division slots) See Figure 33.

3tdv3

2tdv2

1tdv1

0tdv0

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