CS7620 datasheet(62/70 Pages) CIRRUS

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CS7620

DS301PP2

4.53

DAC #1 Control

Default = 00h; Read/Write (address 40h)

4.54

DAC #2 Control

Default = 00h; Read/Write (address 41h)

clk_divide4

Clock Divider: The master clock frequency can be an integer multiple of the

pixel clock rate. This register contains the number by which to divide the mas-

ter clock frequency in order to get the pixel clock frequency. If a ‘0’ is pro-

grammed here, the divider is bypassed and the master clock is assumed to be

at the pixel rate.

clk_divide3

clk_divide2

clk_divide1

clk_divide0

Bit Number

765432

Bit Name

dac_cntl17

dac_cntl16

dac_cntl15

dac_cntl14

dac_cntl13

dac_cntl12

dac_cntl11

dac_cntl10

Default

0000000

Bit

Mnemonic

Function

dac_cntl17

DAC#1 Control: This is the digital input code to the general purpose DAC#1

which will then be converted into the analog current output. Each LSB in this

word will increment the output by ~8.7 µA in low current mode and ~34 µA in

high current mode.

dac_cntl16

dac_cntl15

dac_cntl14

dac_cntl13

dac_cntl12

dac_cntl11

dac_cntl10

Bit Number

765432

Bit Name

dac_cntl27

dac_cntl26

dac_cntl25

dac_cntl24

dac_cntl23

dac_cntl22

dac_cntl21

dac_cntl20

Default

000000

Bit

Mnemonic

Function

dac_cntl27

DAC #2 Control: This is the digital input code to the general purpose DAC#2

which will then be converted into the analog current output. Each LSB in this

word will increment the output by ~8.7 µA in low current mode and ~34 µA in

high current mode.

dac_cntl26

dac_cntl25

dac_cntl24

dac_cntl23

dac_cntl22

dac_cntl21

dac_cntl20

Bit

Mnemonic

Function

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