CS7620 datasheet(65/70 Pages) CIRRUS

65 / 70 page

CS7620

DS301PP2

5.1

Supply

VDDA[1:2] - Supply for analog

Pins 25 and 40

5 V analog supply.

VDDA3 - Supply for horizontal outputs

Pin 32

3.3 V or 5 V analog supply.

VDDD - Supply for digital

Pin 5

5 V digital supply.

VDD_RING - supply for pad ring (digital pads)

Pin 11

3.3 V or 5 V digital supply

5.2

Ground

GNDA[1:2] - Ground for analog

Pins 24 and 41

GNDA1 and GNDA2 are supplied by VDDA1 and VDDA2 respectively.

GNDA3 - Ground for horizontal outputs

Pin 31

Supplied by VDDA3.

GNDD - Ground for digital

Pin 4

Supplied by VDDD.

GND_RING - Ground for pad ring (digital pads)

Pin 10

Supplied by VDD_RING.

5.3

CMOS Input

BYPASS_PLL - Powers down PLL if not in use

Pin 39

Supplied by VDDA2.

CLAMP - Black level clamp signal

Pin 2

Only used if an external timing generator is used. Supplied by VDD_RING.

CLOCK_IN - Chip input clock

Pin 43

Supplied by VDDA2.

EXPOSE - Begin expose sequence

Pin 14

Expose signal from the shutter. Supplied by VDD_RING.

LINE_ENA - Line enable signal

Pin 3

Supplied by VDD_RING.

PWR_DN - Places chip in full power down

Pin 15

Supplied by VDD_RING.

REF_CAPN - Reference capacitor- negative terminal

Pin 27

Supplied by VDDA1. A 1 µF ceramic capacitor should be connected between

REF_CAPN and REF_CAPP.

REF_CAPP - Reference capacitor- positive terminal

Pin 28

Supplied by VDDA1. A 1 µF ceramic capacitor should be connected between

REF_CAPN and REF_CAPP.

CS7620 датащи(PDF) 65 Page - Cirrus Logic

CS7620 датащи(HTML) 65 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL