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CS7620 датащи(PDF) 35 Page - Cirrus Logic |
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CS7620 датащи(HTML) 35 Page - Cirrus Logic |
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35 / 70 page ![]() CS7620 DS301PP2 35 4.12 Gain Calibration - Offset 3 Default = 00h; Read/Write (address 11h) Gain Calibration - Fix Gains Default = 00h; Read/Write (address 16h) Bit Number 765432 10 Bit Name gain_offset 37 gain_offset 36 gain_offset 35 gain_offset 34 gain_offset 33 gain_offset 32 gain_offset 31 gain_offset 30 Default 0 0000000 Bit Mnemonic Function 7 gain_offset37 Gain Calibration Offset 3: Offset added to 1x gain segment. Values are in 2’s complement. These registers are used to report some of the calibration settings. After cal- ibration is performed the gain offset registers are automatically updated with values needed for the DRX circuitry to operate correctly. These registers should not be written to since this will remove the proper settings found during calibration. The gain offset values are used to add an offset to the output of the ADC when using different analog gain settings (See equations below). The purpose of this is to produce a continuous transition between the different gain settings so that the final 13 bit output is monotonic and has no undesired artifacts. (See Figure 26) {ADC_outif in the 8x gain segment} dout[12:0] ={ADC_out*2+Offset1if in the 4x gain segment} {ADC_out*4+Offset2*2if in the 2x gain segment} {ADC_out*8+Offset3*4if in the 1x gain segment} 6 gain_offset36 5 gain_offset35 4 gain_offset34 3 gain_offset33 2 gain_offset32 1 gain_offset31 0 gain_offset30 Bit Number 7 6 543 2 1 0 Bit Name Reserved fixed_gain2 fixed_gain1 fixed_gain0 Reserved Default -- 000 --- Bit Mnemonic Function 7:6 - Reserved 5 fixed_gain2 Fixed Gain: This is used to turn off the DRX functionality and apply a fixed gain to the input before reaching the ADC. A setting of 000 is used for normal operation this will yield the largest dynamic range by switching the front end gain relative to the amplitude of the input signal. The settings 001, 010, 011, and 100 are for fixed gains of 1x, 2x, 4x, and 8x respectively. Figure 27 shows the transfer function of the output of the ADC for a given input with the various fixed gain settings. 4 fixed_gain1 3 fixed_gain0 2:0 - Reserved |
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