CS7620 datasheet(61/70 Pages) CIRRUS

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CS7620

DS301PP2

4.51

Power_up Counter

Default = 7Dh; Read/Write (address 3Dh)

4.52

Valid_data/Dout Edge/Clock_in Divider

Default = 01h; Read/Write (address 3Fh)

Bit Number

765432

Bit Name

cnt_reg7

cnt_reg6

cnt_reg5

cnt_reg4

cnt_reg3

cnt_reg2

cnt_reg1

cnt_reg0

Default

1111101

Bit

Mnemonic

Function

cnt_reg7

Power Up Counter Register: When coming out of power down, there is a pe-

riod of time required for voltages and currents to settle to the proper values,

for the PLL to lock, and for the gain calibration to be performed. This should

all be accomplished within 500 µs. The pixel clocks required to meet this 500

µs time should be programmed into this register. Note that if the master clock

is being divided on chip, the divider’s output clock is the pixel clock.

cnt_reg6

cnt_reg5

cnt_reg4

cnt_reg3

cnt_reg2

cnt_reg1

cnt_reg0

Bit Number

765432

Bit Name

Reserved

valid_data

dout_edge

clk_divide4 clk_divide3 clk_divide2 clk_divide1 clk_divide0

Default

0000001

Bit

Mnemonic

Function

Reserved

valid_data

Valide Data Mode: This mode will redefine the CLKO pin as a data valid pin.

The data_valid signal will only toggle over active pixels and is phase-aligned

with the master clock. The user may then latch the data during this valid time

using the master clock or a clock derived from it. Note that this mode may only

be used if the master clock frequency is an integer multiple greater than 1 of

the pixel rate (see Figures 14 and 15).

If this mode is not selected, the output clock is output on the CLKO pin.

0 - digital clock output on CLKO pin

1 - valid_data signal on CLKO pin

dout_edge

Dout Edge Selelction: If valid_data = 0, the edge of the clock that clocks out

the data is selected by this bit. The data may be output either on the rising or

the falling edge of the output clock, CLKO. HSYNC and RD_OUT are also out-

put on same edge.

Note that If valid_data = “1”, this register is invalid.

* HSYNC and RD_OUT also output on the same edge

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