CS7620 datasheet(31/70 Pages) CIRRUS

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CS7620

DS301PP2

4.5

Operation Control 2

Default = 04h; Read/Write (address 07h).

Bit Number

654

Bit Name

pol_hsyncb

pol_rd_outb

dac2_mode

dac1_mode

fs_lvl1

fs_lvl0

gain_cal1

gain_cal2

Default

Bit

Mnemonic

Function

pol_hsyncb

Hsync Polarity: The HSYNC signal output from the chip defaults to be high

when data is being shifted out of the CCD and low during all other times (the

vertical shift time of each line and idle times). This polarity may be swapped

with this bit so that HSYNC is low when data is being shifted out and high all

other times.

0 - HSYNC is high during horizontal data read out

1 - HSYNC is low during horizontal data read out

pol_rd_outb

Rd_Out Polarity: The RD_OUT signal output from the chip defaults to be low

when the CCD data readout is being performed and high when not reading out

data from the CCD. The polarity of this signal may be swapped with this bit so

that RD_OUT is high during readout and low when not reading data out. Note

that when this bit is redefined in order to function as a vertical sync signal, this

bit will serve to swap its polarity as well.

dac2_mode

Dac #2 Current Mode: There are two modes for the output current of DAC2.

Default mode provides a current range of 2.2 mA for the 8-bit input word. This

will increment the current by ~8.6 µA per LSB code change. The high current

mode can be selected using this bit to change the current range to 8.7 mA for

the 8-bit input word. This will increment the current by ~34 µA per LSB code

change.

dac1_mode

Dac #1 Current Mode: There are two modes for the output current of DAC1.

Default mode provides a current range of 2.2 mA for the 8-bit input word. This

will increment the current by ~8.6 µA per LSB code change. The high current

mode can be selected using this bit to change the current range to 8.7 mA for

the 8-bit input word. This will increment the current by ~34 µA per LSB code

change.

fs_lvl1

Full Scale Level: This is used to set the full scale input range of the CS7620.

Since CCDs have various saturation levels, it is advantageous to set the full

scale input range of the CS7620 to match the saturation level of the CCD

used. Table 9 shows the full scale level choices

fs_lvl0

gain_cal1

Gain Calibration #1: A calibration of the gain stages is required to insure a

monotonic digital output. In default (‘0’), this calibration is automatically done

after a chip reset and after coming up from power down mode. If the recalibra-

tion after power down is not desired, this bit can be written with a ‘1’ to force

a calibration only after a chip reset.

gain_cal2

Gain Calibration #2: A calibration of the gain stages is required to insure a

monotonic digital output. This calibration is transparent to the user. However,

if the user wishes to force a calibration to occur, he may do so by setting this

bit to ‘1’, which will invoke a gain calibration sequence immediately. This bit

automatically clears itself after a calibration has been initiated.

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