CS7620 datasheet(66/70 Pages) CIRRUS

66 / 70 page

CS7620

DS301PP2

RST - Reset pin, negative true

Pin 38

May be connected to external power-on-reset-circuit. Supplied by VDDA2.

SCAN_MODE - Test

Pin 17

Supplied by VDD_RING.

SCLK - Serial bus clock signal

Pin 6

Supplied by VDD_RING.

SDATI - Serial bus data input signal

Pin 7

Supplied by VDD_RING.

SEN - Serial bus enable signal-chip select (active low)

Pin 9

Supplied by VDD_RING.

TEST - Test enable pin

Pin 16

Supplied by VDD_RING.

5.4

CMOS Analog Input

AIN - Video data input from CCD

Pin 23

Supplied by VDDA1.

BG_RES - Band-gap resistor

Pin 21

Supplied by VDDA1. A 10 k

Ω resistor should be connected between BG_RES

and GNDA1.

5.5

CMOS Analog Output

DAC_OUT[1:2] - General purpose Digital-to-Analog converter output

Pins 18 and 19

Supplied by VDDA1.

5.6

CMOS 4 mA Output

CLKO - Clock = output

Pin 52

Signal on this pin can either be the pixel clock output or data_valid signal out-

put. Supplied by VDD_RING.

DOUT[0:12] - Digitized CCD data output

Pins 53-64, and 1

DOUT0 is LSB. Supplied by VDD_RING.

SDATO - Serial bus data output signal

Pin 8

Supplied by VDD_RING.

HSYNC - Horiz sync (active low)

Pin 12

Supplied by VDD_RING.

RD_OUT - Readout signal (active low)

Pin 13

Supplied by VDD_RING.

RG - Reset gate clock pulse for CCD

Pin 37

Supplied by VDDA3.

CS7620 датащи(PDF) 66 Page - Cirrus Logic

CS7620 датащи(HTML) 66 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL