CS7620 datasheet(41/70 Pages) CIRRUS

41 / 70 page

CS7620

DS301PP2

4.20

Timing Control - Number of Rows until Active

Default = C6h; Read/Write (address 1Eh)

Bit Number

765432

Bit Name

act_rws_frst3 act_rws_frst2 act_rws_frst1 act_rws_frst0 act_rws_lst3

act_rws_lst2

act_rws_lst1

act_rws_lst0

Default

1000110

Bit

Mnemonic

Function

7act_rws_frst3

Active Rows: act_rws_frst corresponds to the first group of non active rows

at the top of the image, which get inverted through the lens, and get focused

onto the bottom rows of the CCD.

The register value is used by the CS7620 when the part is in the valid data

mode to generate the data valid signal on the CLKO pin.

Valid data can be set through the above mentioned registers together with

act_begin(1Fh) to define a subset of pixels to be passed to the subsequent

ASIC or DSP component. This subset may or may not include dark rows

and/or dark pixels. Please refer to Figure 28.

6act_rws_frst2

5act_rws_frst1

4act_rws_frst0

act_rws_lst3

Active Rows: act_rws_lst corresponds to the last group of non active rows at

the bottom of the image, which get inverted through the lens, and get focused

onto the top rows of the CCD.

The register value is used by the CS7620 when the part is in the valid data

mode to generate the data valid signal on the CLKO pin.

Valid data can be set through the above mentioned registers together with

act_begin(1Fh) to define a subset of pixels to be passed to the subsequent

ASIC or DSP component. This subset may or may not include dark rows

and/or dark pixels. Please refer to Figure 28.

act_rws_lst2

act_rws_lst1

act_rws_lst0

drk_rws_lst (1Bh)

blk_begin (1Ch)

blk_end (1Dh)

Dark Pixels

act_rws_lst (1Eh)

num_pixels (19h, 1Ah)

num_lines (17h, 18h)

act_rws_frst (1Eh)

shiftl_num (21h, 22h)

drk_rws_frst (1Bh)

ACTIVE PIXELS

TRANSFER

AREA

Figure 28. Typical CCD Pixel Arrangement

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