DSP56857 datasheet(130/662 Pages) FREESCALE

130 / 662 page

Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

5-4

Freescale Semiconductor

5.3 Functional Description

The 56800E core architecture contains three separate buses for access to memory/peripherals.

The EMI attaches to all of these buses and provides an interface to external memory over a single

external bus. The EMI serializes these internal requests to external memory in a manner avoiding

conflicts and contention.

5.3.1 Core Interface Detail

Managing the core access to the external memory consists of four issues: (Please refer to

Figure 5-1.)

1. Any of the three buses can request external access at any time. This means the EMI can

potentially have three requests it must be completed before the core can proceed. The EMI

must hold-off further execution of the core until it can serialize the requests over the

external bus. This provides simultaneous data for all buses to the core for read operations.

2. There may be a mixture of read and write requests on the core buses. For instance, the

program memory bus may request a read operation while the primary data bus (XAB1) is

requesting a write operation.

3. The primary data bus (XAB1) may request an 8-bit transfer. This request must access the

appropriate external byte.

4. The primary data bus (XAB1) may request a 32-bit transfer. This request requires two

accesses of the external bus. The EMI must hold-off further core execution until all 32 bits

have been transferred. This action may happen in conjunction with item one above.

DSP56857 датащи(PDF) 130 Page - Freescale Semiconductor, Inc