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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56857 датащи(PDF) 103 Page - Freescale Semiconductor, Inc |
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DSP56857 датащи(HTML) 103 Page - Freescale Semiconductor, Inc |
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103 / 662 page  Memory Maps Overview, Rev. 4 Freescale Semiconductor 3-15 Table 3-16. Enhanced Synchronous Serial Interface 0 Registers Address Map (ESSI0_BASE = $1FFE20) see Chapter 12 Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 ESSI_0_STX0 Transmit Register 0 Write-Only Section 12.8.1 Base + $1 ESSI_0_STX1 Transmit Register 1 Write-Only Section 12.8.2 Base + $2 ESSI_0_STX2 Transmit Regsiter 2 Write-Only Section 12.8.3 Base + $3 ESSI_0_SRX Receive Register Read-Only Section 12.8.4 Base + $4 ESSI_0_SSR Status Register Read-Only Section 12.8.7 Base + $5 ESSI_0_SCR2 Control Register 2 Read/Write Section 12.8.8 Base + $6 ESSI_0_SCR3 Control Register 3 Read/Write Section 12.8.9 Base + $7 ESSI_0_SCR4 Control Register 4 Read/Write Section 12.8.10 Base + $8 ESSI_0_STXCR Transmit Control Register Read/Write Section 12.8.11 Base + $9 ESSI_0_SRXCR Receive Control Register Read/Write Base + $A ESSI_0_STSR Time Slot Register Write-Only Section 12.8.12 Base + $B ESSI_0_SFCSR FIFO Control / Status Register Read-Only Section 12.8.13 Base + $C ESSI_0_TSMA Transmit Slot Mask Register Read/Write Section 12.8.14 Base + $D ESSI_0_TSMB Transmit Slot Mask Register Read/Write Base + $E ESSI_0_RSMA Receive Slot Mask Register Read/Write Section 12.8.15 Base + $F ESSI_0_RSMB Receive Slot Mask Register Read/Write Table 3-17. Enhanced Synchronous Serial Interface 1 Registers Address Map (ESSI1_BASE =$1FFE00) see Chapter 12 Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 ESSI_1_STX0 Transmit Register 0 Write-Only Section 12.8.1 Base + $1 ESSI_1_STX1 Transmit Register 1 Write-Only Section 12.8.2 Base + $2 ESSI_1_STX2 Transmit Regsiter 2 Write-Only Section 12.8.3 Base + $3 ESSI_1_SRX Receive Register Read-Only Section 12.8.4 Base + $4 ESSI_1_SSR Status Register Read-Only Section 12.8.7 Base + $5 ESSI_1_SCR2 Control Register 2 Read/Write Section 12.8.8 Base + $6 ESSI_1_SCR3 Control Register 3 Read/Write Section 12.8.9 Base + $7 ESSI_1_SCR4 Control Register 4 Read/Write Section 12.8.10 Base + $8 ESSI_1_STXCR Transmit Control Register Read/Write Section 12.8.11 Base + $9 ESSI_1_SRXCR Receive Control Register Read/Write Base + $A ESSI_1_STSR Time Slot Register Write-Only Section 12.8.12 Base + $B ESSI_1_SFCSR FIFO Control / Status Register Read-Only Section 12.8.13 Base + $C ESSI_1_TSMA Transmit Slot Mask Register Read/Write Section 12.8.14 Base + $D ESSI_1_TSMB Transmit Slot Mask Register Read/Write Base + $E ESSI_1_RSMA Receive Slot Mask Register Read/Write Section 12.8.15 Base + $F ESSI_1_RSMB Receive Slot Mask Register Read/Write |
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