S70FS01GS datasheet(21/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 21 of 141

3.3.14

Quad Input Cycle - Host to Memory Transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. In QPI mode the Quad I/O Read and

Page Program commands transfer four data bits to the memory in each cycle, including the instruction cycles. The host keeps CS#

low, and drives the IO signals.

For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are

latency cycles needed or Quad Output Cycle if no latency is required. For QPI mode Page Program, the host returns CS# high

following the delivery of data to be programmed and the interface returns to standby state.

3.3.15

Quad Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main Flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR2V[3:0]).

During the latency cycles, the host keeps CS# low. The host may drive the IO signals during these cycles or the host may leave the

IO floating. The memory does not use any data driven on IO during the latency cycles. The host must stop driving the IO signals on

the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents

driver conflict between host and memory when the signal direction changes. The memory does not drive the IO signals during the

latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

3.3.16

Quad Output Cycle - Memory to Host Transfer

The Quad I/O Read returns data to the host four bits in each cycle. The host keeps CS# low. The memory drives data on IO0-IO3

signals during the Quad output cycles.

The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the command.

3.3.17

DDR Quad Input Cycle - Host to Memory Transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four bits are transferred on

the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps CS# low.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.18

DDR Latency Cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main Flash memory array

before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register

(CR2V[3:0]). During the latency cycles, the host keeps CS# low. The host may not drive the IO signals during these cycles. So that

there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between host

and memory when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern

(DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so that

there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP. When

there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles of latency.

The next interface state following the last latency cycle is a DDR Single, or Quad Output Cycle, depending on the instruction.

3.3.19

DDR Quad Output Cycle - Memory to Host Transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Four bits are transferred on the rising edge of SCK

and four bits on the falling edge in each cycle. The host keeps CS# low.

The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the command.

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