S70FS01GS datasheet(53/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 53 of 141

Address Length Non-volatile CR2NV[7]:

This bit controls the POR, hardware reset, or software reset state of the expected

address length for all commands that require address and are not fixed 3 byte only or 4 Byte (32 bit) only address. Most commands

that need an address are legacy SPI commands that traditionally used 3 byte (24 bit) address. For device densities greater than

128 Mbit a 4 Byte address is required to access the entire memory array. The address length configuration bit is used to change

most 3 Byte address commands to expect 4 Byte address. See Table 9.1, FS-S Family Command Set (sorted by function)

on page 74 for command address length. This non-volatile Address Length configuration bit enables the device to start immediately

(boot) in 4 Byte address mode rather than the legacy 3 Byte address mode.

QPI Non-volatile CR2NV[6]:

This bit controls the POR, hardware reset, or software reset state of the expected instruction width for

all commands. Legacy SPI commands always send the instruction one bit wide (serial I/O) on the SI (IO0) signal. The FS-S Family

also supports the QPI mode in which all transfers between the host system and memory are 4 bits wide on IO0 to IO3, including all

instructions. This non-volatile QPI configuration bit enables the device to start immediately (boot) in QPI mode rather than the legacy

serial instruction mode. When this bit is programmed to QPI mode, the QUAD_NV bit is also programmed to Quad mode

(CR1NV[1]=1). The recommended procedure for moving to QPI mode is to first use the WRAR command to set CR2V[6]=1, QPI

mode. The volatile register write for QPI mode has a short and well defined time (tCS) to switch the device interface into QPI mode.

Following commands can then be immediately sent in QPI protocol. The WRAR command can be used to program CR2NV[6]=1,

followed by polling of SR1V[0] to know when the programming operation is completed. Similarly, to exit QPI mode, the WRAR

command is used to clear CR2V[6]=0. CR2NV[6] cannot be erased to 0 because it is OTP.

IO3 Reset Non-volatile CR2NV[5]:

This bit controls the POR, hardware reset, or software reset state of the IO3 signal behavior.

Most legacy SPI devices do not have a hardware reset input signal due to the limited signal count and connections available in

traditional SPI device packages. The FS-S Family provides the option to use the IO3 signal as a hardware reset input when the IO3

signal is not in use for transferring information between the host system and the memory. This non-volatile IO3 Reset configuration

bit enables the device to start immediately (boot) with IO3 enabled for use as a RESET# signal.

Read Latency Non-volatile CR2NV[3:0]:

This bit controls the POR, hardware reset, or software reset state of the read latency

(dummy cycle) delay in all variable latency read commands. The following read commands have a variable latency period between

the end of address or mode and the beginning of read data returning to the host:



Fast Read



Dual I/O Read



Quad I/O Read



DDR Quad I/O Read



OTPR



ECCRD



RDAR

This non-volatile read latency configuration bit sets the number of read latency (dummy cycles) in use so the device can start

immediately (boot) with an appropriate read latency for the host system.

Table 7.11

Latency Code (Cycles) Versus Frequency

Latency Code

Read Command Maximum Frequency (MHz)

Fast Read (1-1-1)

OTPR (1-1-1)

RDAR (1-1-1)

RDAR (4-4-4)

Dual I/O (1-2-2)

Quad I/O (1-4-4)

Quad I/O (4-4-4)

DDR Quad I/O (1-4-4)

DDR Quad I/O (4-4-4) (Note 4)

Mode Cycles = 0

Mode Cycles = 4

Mode Cycles = 2

Mode Cycles = 1

508040

N/A

66925322

104

116

104

129

116

133

104

129

133

116

133

129

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