S70FS01GS datasheet(50/141 Pages) CYPRESS

50 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 50 of 141

7.7.3

Configuration Register 1

Configuration register 1 controls certain interface and data protection functions. The register bits can be changed using the WRAR

command.

7.7.3.1

Configuration Register 1 Non-volatile (CR1NV)

Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).

Top or Bottom Protection (TBPROT_O) CR1NV[5]:

This bit defines the operation of the Block Protection bits BP2, BP1, and BP0

in the Status Register. As described in the status register section, the BP2-0 bits allow the user to optionally protect a portion of the

array, ranging from 1/64, ¼, ½, etc., up to the entire array. When TBPROT_O is set to a “0” the Block Protection is defined to start

from the top (maximum address) of the array. When TBPROT_O is set to a “1” the Block Protection is defined to start from the

bottom (zero address) of the array. The TBPROT_O bit is OTP and set to a “0” when shipped from Cypress. If TBPROT_O is

programmed to 1, writing the bit with a zero does not change the value or set the Program Error bit (P_ERR in SR1V[6]).

The desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture; before

the first program or erase operation on the main Flash array. TBPROT_O must not be programmed after programming or erasing is

done in the main Flash array.

When Read Password Mode is active, TBPROT_O also selects the boot address range that is readable after power on reset. When

TBPROT_O is cleared to a “0” the bottom (zero address) 256 KB of the array is readable. When TBPROT_O is set to a “1” the top

(maximum address) 256 KB of the array is readable.

CR1NV[4]:

Reserved for Future Use

Block Protection Non-Volatile (BPNV_O) CR1NV[3]

: The BPNV_O bit defines whether the BP_NV 2-0 bits or the BP 2-0 bits in

the Status Register are selected to control the Block Protection feature. The BPNV_O bit is OTP and cleared to a “0” with the BP_NV

bits cleared to “000” when shipped from Cypress. When BPNV_O is set to a “0” the BP_NV 2-0 bits in the Status Register are

selected to control the block protection and are written by the WRR command. The time required to write the BP_NV bits is tW.

When BPNV is set to a “1” the BP2-0 bits in the Status Register are selected to control the block protection and the BP_NV 2-0 bits

will be programmed to binary “111”. This will cause the BP 2-0 bits to be set to binary 111 after POR, hardware reset, or command

reset. When BPNV is set to a 1, the WRR command writes only the volatile version of the BP bits (SR1V[4:2]). The non-volatile

version of the BP bits (SR1NV[4:2]) are no longer affected by the WRR command. This allows the BP bits to be written an unlimited

number of times because they are volatile and the time to write the volatile BP bits is the much faster tCS volatile register write time.

If BPNV_O is programmed to 1, writing the bit with a zero does not change the value or set the Program Error bit (P_ERR in

SR1V[6]).

Table 7.8

Configuration Register 1 Non-volatile (CR1NV)

Bits

Field Name

Function

Type

Default

State

Description

RFU

Reserved for Future Use

Non-volatile

Reserved

RFU

TBPROT_O

Configures Start of Block

Protection

and selects readable boot

sector in Read Password

Mode

OTP

1 = BP starts at bottom (Low address)

0 = BP starts at top (High address)

RFU

Reserved for Future Use

OTP

Reserved for Future Use

BPNV_O

Configures BP2-0 in

Status Register

OTP

1 = Volatile

0 = Non-Volatile

TBPARM_O

Configures Parameter

Sectors location

OTP

1 = 4 KB physical sectors at top, (high address)

0 = 4 KB physical sectors at bottom (Low address)

RFU in uniform sector configuration.

QUAD_NV

Quad Non-Volatile

Non-Volatile

Provides the default state for the QUAD bit.

FREEZE_D

FREEZE Default

Non-Volatile

Read Only

Provides the default state for the Freeze bit. Not user programmable.

S70FS01GS датащи(PDF) 50 Page - Cypress Semiconductor

S70FS01GS датащи(HTML) 50 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL