S70FS01GS datasheet(5/141 Pages) CYPRESS

5 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 5 of 141

1.2.2.8

Separate Reset Input Not Supported

In some legacy SPI devices, a separate hardware RESET# input is supported in packages having more than 8 connections. The FS-

S family does not support a separate RESET# input. The FS-S family provides an alternate function for the IO3 input as a RESET#

input. When the CS# signal is high and the IO3/Reset feature is enabled, the IO3/RESET# input is used to initiate a hardware reset

when the input goes low.

1.2.2.9

Other Legacy Commands Not Supported



Autoboot Related Commands



Bank Address Related Commands



Dual Output Read



Quad Output Read



Quad Page Program (QPP) - replaced by Page Program in QPI mode



DDR Fast Read



DDR Dual I/O Read



Write Register



Read Configuration Register



Read Status Register 1



Read Status Register 2



Program NV Data Learning Register



ASP Program



Password Program



PPB Erase



Erase Program Suspend (B0h)



Erase Program Resume (30h)

1.2.2.10

New Features

The FS-S family introduces new features to Cypress SPI category memories:



Single 1.8V power supply for core and I/O voltage.



Configurable initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read

commands



QPI (QPI, 4-4-4) read mode in which all transfers are 4 bits wide, including instructions



JEDEC JESD216 standard, Serial Flash Discoverable Parameters (SFDP) that provide device feature and configuration

information.



Evaluate Erase Status command to determine if the last erase operation on a sector completed successfully. This

command can be used to detect incomplete erase due to power loss or other causes. This command can be helpful to

Flash File System software in file system recovery after a power loss.



Advanced Sector Protection (ASP) Permanent Protection. A bit is added to the ASP register to provide the option to make

protection of the Persistent Protection Bits (PPB) permanent. Also, when one of the two ASP protection modes is selected,

all OTP configuration bits in all registers are protected from further programming so that all OTP configuration settings are

made permanent. The OTP address space is not protected by the selection of an ASP protection mode. The Freeze bit

(CR1V[0]) may be used to protect the OTP Address Space.



Single Chip Select (CS#) Dual Die Package (DDP) density option that uses two FS512S devices stacked within the same

package to provide 1Gbit of memory. The the two devices share the CS# input to provide a contiguous 1 Gbit (128 MByte)

address space. However, there are some behavior and software differences from the other members of the FS-S family

that are described in Section 12.4 FS01GS Behavior and Software Modifications on page 134.

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