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S70FS01GS датащи(PDF) 75 Page - Cypress Semiconductor |
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S70FS01GS датащи(HTML) 75 Page - Cypress Semiconductor |
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75 / 141 page ![]() S70FS01GS Document Number: 002-03833 Rev. *C Page 75 of 141 Notes 1. Commands not supported in QPI mode have undefined behavior if sent when the device is in QPI mode. 2. The FS01GS does not support some commands and adds some commands. For additional information see Section 12.4 FS01GS Behavior and Software Modifications on page 134. 9.1.4 Read Device Identification There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories from different vendors have used different commands and formats for reading information about the memories. The FS-S Family supports the three device information commands. 9.1.5 Register Read or Write There are multiple registers for reporting embedded operation status or controlling device configuration options. There are commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Non-volatile bits in registers are automatically erased and programmed as a single (write) operation. 9.1.5.1 Monitoring Operation Status The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command or Read Any Register command provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether the most recent program or erase command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy and unable to receive most new operation commands. Only Read Any Register (RDAR 65h), status clear (CLSR 30h or 82h), and software reset (RSTEN 66h, RST 99h or RESET F0h) are valid commands when P_ERR or E_ERR is set to 1. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to standby state. Clear Status Register clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software Reset (RST or RESET) may be used to return the device to standby state. Advanced Sector Protection DYBRD DYB Read FA 133 3 or 4 Yes 4DYBRD DYB Read E0 133 4 Yes DYBWR DYB Write FB 133 3 or 4 Yes 4DYBWR DYB Write E1 133 4 Yes PPBRD PPB Read FC 133 3 or 4 No 4PPBRD PPB Read E2 133 4 No PPBP PPB Program FD 133 3 or 4 No 4PPBP PPB Program E3 133 4 No PPBEA PBB Erase Addressed EA 133 4 No ASPRD ASP Read 2B 133 0 No PLBRD PPB Lock Bit Read A7 133 0 No PLBWR PPB Lock Bit Write A6 133 0 No PASSRD Password Read E7 133 0 No PASSU Password Unlock E9 133 0 No Reset RSTEN Software Reset Enable 66 133 0 Yes RST Software Reset 99 133 0 Yes RESET Legacy Software Reset F0 133 0 No MBR Mode Bit Reset FF 133 0 Yes DPD DPD Enter Deep Power Down Mode B9 133 0 Yes RES Release from Deep Power Down Mode AB 133 0 Yes Table 9.1 FS-S Family Command Set (sorted by function) (Continued) Function Command Name Command Description instruction Value (Hex) Maximum Frequency (MHz) Address Length (Bytes) QPI |
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