S70FS01GS datasheet(3/141 Pages) CYPRESS

3 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 3 of 141

Overview

1.1

General Description

The Cypress FS-S Family devices are Flash non-volatile memory products using:



MirrorBit technology - that stores two data bits in each memory array transistor



Eclipse architecture - that dramatically improves program and erase performance



65 nm process lithography

The FS-S Family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output

(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) or QPI, also known as

Quad Peripheral Interface (QPI) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, there are

Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.

The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512-bytes to be programmed in one operation,

resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

Executing code directly from Flash memory is often called Execute-In-Place or XIP. By using FS-S Family devices at the higher

clock rates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel

interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.

The FS-S Family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or

embedded applications. They are an excellent solution for systems with limited space, signal connections, and power. They are ideal

for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.

The S70FS01GS device is a dual die stack of two FS512S die.

1.2

Migration Notes

1.2.1

Features Comparison

The FS-S Family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families. However, the

power supply and interface voltages are nominal 1.8V.

Table 1.1

Cypress SPI Families Comparison

Parameter

FS-S

FL-S

Technology Node

65nm

Architecture

MirrorBit® Eclipse™

Release Date

2H2015

2H2011

Density

1Gbit

1GB

Bus Width

x1, x2, x4

Supply Voltage

1.7V - 2.0V

2.7V - 3.6V / 1.65V - 3.6V VIO

Normal Read Speed (SDR)

6MB/s (50MHz)

Fast Read Speed (SDR)

16.5MB/s (133MHz)

17MB/s (133MHz)

Dual Read Speed (SDR)

33MB/s (133MHz)

26MB/s (104MHz)

Quad Read Speed (SDR)

66MB/s (133MHz)

52MB/s (104MHz)

Quad Read Speed (DDR)

80MB/s (80MHz)

Program Buffer Size

256B / 512B

Erase Sector Size

256KB

Parameter Sector Size

4KB (option)

Sector Erase Rate (typ.)

500 KB/s

Page Programming Rate (typ.)

0.71 MB/s (256B)

1.08 MB/s (512B)

1.0 MB/s (256B)

1.5 MB/s (512B)

OTP

1024B

S70FS01GS датащи(PDF) 3 Page - Cypress Semiconductor

S70FS01GS датащи(HTML) 3 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL