TSB41BA3APFP datasheet(31/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

using the TSB41BA3A with a 1394-1995 or 1394a-2000 link layer

The TSB41BA3A implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based

upon the interface described in Section 17 of IEEE 1394b-2002. When using a LLC compliant with this interface,

the BMODE input must be tied high.

The TSB41BA3A also functions with a LLC that is compliant with the older 1394 standards. This interface is

compatible with both the older Annex J interface specified in the IEEE Std 1394-1995 (with the exception of the

Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a-2000. When using a LLC

compliant with this interface, the BMODE input must be tied low.

When the BMODE input is tied low, the TSB41BA3A implements the PHY-LLC interface specified in the

1394a-2000 Supplement. This interface is based upon the interface described in informative Annex J of IEEE

Std 1394-1995, which is the interface used in the oldest Texas Instruments PHY devices. The PHY-LLC

interface specified in 1394a-2000 is compatible with the older Annex J. However, the TSB41BA3A does not

support the Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals

are not used:

−

The PINT output (terminal 1) may be left open.

−

The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 k

Ω

or less, unless the PMC mode is desired (see LCLK_PMC terminal description).

All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output

corresponds to the SCLK input signal on most LLCs.

The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended

when using the TSB41BA3A with a 1394-1995 LLC device.

D A new LLC service request was added which allows the LLC to temporarily enable and disable

asynchronous arbitration accelerations. If the LLC does not implement this new service request, then the

arbitration enhancements must not be enabled (see the EAA bit in PHY register 5).

D The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was

added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not

support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the

EMC bit in PHY register 5).

D In order to accommodate the higher transmission speeds expected in future revisions of the standard,

1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus

request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY

and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices

that use the 2-bit speed codes. The TSB41BA3A correctly interprets both 7-bit bus requests (with 2-bit

speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately

followed by another request (for example, a register read or write request), then the TSB41BA3A correctly

interprets both requests. Although the TSB41BA3A correctly interprets 8-bit bus requests, a request with

a speed code exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB41BA3A

transmitting a null packet (data-prefix followed by data-end, with no data in the packet).

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