TSB41BA3APFP datasheet(5/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description (continued)

The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal

definition) and is considered active otherwise. When the TSB41BA3A detects that the LPS input is inactive, the

PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic

0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low

for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into

a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3A continues the

necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC

interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the

PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled

state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having

entered the LPS_DISABLE time, the TSB41BA3A issues a bus reset. This broadcasts the node self-ID packet,

which contains the updated L bit state (the PHY LLC now being accessible).

The PHY uses the S5_LKON terminal to notify the LLC to power up and become active. When activated, the

output S5_LKON signal is a square wave. The PHY activates the S5_LKON output when the LLC is inactive

and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described

above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node

is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON output when the

LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the

S5_LKON output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause

S5_LKON to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts

S5_LKON for approximately 167

µs or until both the LPS is active and the LCtrl bit is 1.

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