TSB41BA3APFP datasheet(53/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394B INTERFACE)

LLC service request (continued)

Table 27. Bus Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1−4

Request type

Indicates the type of bus request. See Table 26.

Request format

Indicates the packet format to be used for packet transmission. See Table 28.

6−9

Request speed

Indicates the speed at which the link sends the data to the PHY. See Table 29 for the encoding of this field.

Stop bit

Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit may be omitted.

Table 28 shows the 1-bit request format field used in bus requests.

Table 28. Bus Request Format Encoding

LR5

DATA RATE

Link does not request either beta or legacy packet format for bus transmission

Link requests beta packet format for bus transmission

Table 29 shows the 4-bit request speed field used in bus requests.

Table 29. TBus Request Speed Encoding

LR6−LR9

DATA RATE

0000

S100

0001

Reserved

0010

S200

0011

Reserved

0100

S400

0101

Reserved

0110

S800

All Others

Invalid

NOTE:

The TSB41BA3A accepts a bus request with an invalid speed code and processes the bus request

normally. However, during packet transmission for such a request, the TSB41BA3A ignores any

data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 30.

Table 30. Read Register Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1−4

Request type

A 1010 indicates this is a read register request

5−8

Address

Identifies the address of the PHY register to be read

Stop bit

Indicates the end of the transfer (always 0)

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