TSB41BA3APFP datasheet(43/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

receive (continued)

The sequence of events for a normal packet reception is as follows:

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a

status transfer operation that is in progress so that the CTL lines may change from status to receive without

an intervening idle.

(b) Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles

preceding the speed-code.

for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive cycle

for which the D lines are not the data-on code. If the speed-code is invalid or indicates a speed higher that

that which the link is capable of handling, then the link must ignore the subsequent data.

(d) Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet data

on the D lines with receive on the CTL lines for the remainder of the receive operation.

(e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

(a)

(b)

(c)

FF (data-on)

D0–D7

CTL0, CTL1

SYSCLK

Figure 16. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a

status transfer operation that is in progress so that the CTL lines may change from status to receive without

an intervening idle.

(b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

The PHY asserts at least one idle cycle following a receive operation.

Table 21. Receive Speed Codes

D0−D7

DATA RATE

00XX XXXX

S100

0100 XXXX

S200

0101 0000

S400

11YY YYYY

data-on indication

NOTE: X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

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