TSB41BA3APFP datasheet(40/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

LLC service request (continued)

To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception

of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received

packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY

immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the

header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but

instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant

to send another type of packet. After the interface is released the LLC may proceed with another request.

The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq,

IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request

was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted

control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are

cleared upon a bus reset.

For write register requests, the PHY loads the specified data into the addressed register as soon as the request

transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the

LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the

PHY continues to attempt the transfer of the requested register until it is successful. A write or read register

request may be made at any time, including while a bus request is pending. Once a read register request is

made, the PHY ignores further read register requests until the register contents are successfully transferred to

the LLC. A bus reset does not clear a pending read register request.

The TSB41BA3A includes several arbitration acceleration enhancements, which allow the PHY to improve bus

performance and throughput by reducing the number and length of interpacket gaps. These enhancements

include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet

concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following

acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.

The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit

the cycle start message under certain circumstances. The acceleration control request is therefore provided

to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41BA3A

during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter

rolls over indicating that a cycle start message is imminent, and then re-enables the enhancements when it

receives a cycle start message. The acceleration control request may be made at any time and is immediately

serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be

re-enabled, if the EAA bit is set.

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