TSB41BA3APFP datasheet(11/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

TYPE

PFP

NO.

GGM

NO.

I/O

DESCRIPTION

CMOS

Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD

input high also activates an internal pulldown on the RESETz terminal to force a reset of the

internal control logic.

PINT

CMOS

PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information

to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this

terminal.

PLLGND

Supply

25,

G9,

−

PLL circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

PLLVDD-CORE

Supply

29,

F8,

−

PLL core circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. An additional

µF capacitor is required for voltage regulation. The PLLVDD-CORE terminals must be

separate from the DVDD-CORE terminals. These supply terminals are separated from the

DVDD-CORE, DVDD-3.3, PLLVDD-3.3 and AVDD-3.3 terminals internal to the device to

provide noise isolation.

PLLVDD-3.3

Supply

−

PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors

near the terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. Lower frequency

10-

µF filtering capacitors are also recommended. This supply terminal is separated from the

DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device

to provide noise isolation. The DVDD-3.3 terminals must be tied together at a

low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3

terminals must be tied together with a low dc impedance connection.

RESETz

CMOS

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup

resistor to VDD is provided so only an external delay capacitor is required for proper

power-up operation (see power-up reset in the APPLICATIONS INFORMATION section).

The RESETz terminal also incorporates an internal pulldown which is activated when the

PD input is asserted high. This input is otherwise a standard logic input, and can also be

driven by an open-drain type driver.

Bias

J10

−

Current setting resistor terminals. These terminals are connected to a precision external

resistance to set the internal operating currents and cable driver output currents. A

resistance of 6.34 k

Ω ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.

CMOS

D10

Test control input. This input is used in the manufacturing test of the TSB41BA3A. For

normal use this terminal must be pulled low either through a 1-k

Ω resistor to GND or directly

to GND.

SLPEN

CMOS

Automotive sleep mode enable input. This terminal enables the automotive sleep mode.

When deasserted (logic low), normal 1394.b functionality is maintained.

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3A. For

normal use this terminal must be pulled low either through a 1-k

Ω resistor to GND or directly

to GND.

S2_PC0

S1_PC1

S0_PC2

CMOS

Port sleep/mode selection terminals 2−0 and power class programming. On hardware

reset, this terminal when used with the other 5 selection pins allows the user to select the

speed and mode of the ports. See Table 1. Depending on the selection these inputs may set

the default value of the power class indicated during self-ID.

Programming is done by tying the terminals high through a 1-k

Ω or smaller resistor or by

tying directly to ground through a 1-k

Ω or smaller resistor. Bus holders are built into these

terminals.

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